Double-Gate MOSFETs: Is Gate Alignment Mandatory?

Abstract

Double-gate (DG) MOSFETs promise to enhance transistor capabilities beyond the limits of conventional CMOS technology.In this paper, we study for the first time the impact of gate misalignment in "non-ideal" DG devices that may be much easier to fabricate than self-aligned versions.Drain current, transconductance, series resistance effects, subthreshold slope and carrier concentration profiles are simulated for different architectures, based on a 50nm long SOI MOSFET. We compare single gate, ideal aligned DG, and non-aligned DG transistors in which unequal gate lengths are used to compensate for the gate misalignment. We find that non-aligned DG devices are competitive with and even, in some cases, superior to ideal DG MOS, albeit with unusual g m curves.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

“…11a) [29]. Although an oversize DG device operating in the subthreshold region can control the channel potential more effectively as compared to a misaligned gate, the additional parasitic capacitance degrades the analog/rf performance.…”

“…0038 Our previous study on underlap design in vertical FinFETs [20,21] for ULV applications has shown significant improvement in analog/rf figures of merit (FOM). Earlier work [29][30][31] focusing on digital applications featuring gate misalignment in DG devices with non-underlap S/D extension regions predicted severe short channel effects and degraded subthreshold behavior. This degradation in weak inversion region lowers transconductance-to-current ratio (g m /I ds ) and precludes use for ULV analog/rf applications.…”

A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

“…Of these, the back-gate planar configuration [18] may result in the densest cell layout for this particular application. Although achieving close alignment between the gates still represents a major processing hurdle, process flows for planar DG-MOSFET with selfaligned top and bottom gates have already been demonstrated [12], [18], and there is evidence to suggest that adequate performance might be achieved without precise gate alignment [19]. Although these devices have focussed on conventionally doped source/drain devices, an alternative using silicide source/drain regions and a mid-band metal gate structure may offer some advantages and this is briefly explored in Section II-B.…”

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

“…The circuit with has the smallest PDP among all the ring oscillators simulated. Our simulation results suggest that the circuit speed will be further improved for DG-SOI with the bottom gate smaller than that of the top gate [16]. The concept is similar to the gate nonoverlapped structure [17].…”