No abstract

Based on 3D simulations, we report a performance assessment of triple-and double-gate FinFETs for high performance (HP), low operating power (LOP) and low standby power (LSTP) logic technologies according to ITRS 65 nm node specifications. The impact of spacer width, lateral source/drain doping gradient, aspect ratio, fin thickness and height along with gate work function on the device performance has been analysed in detail and guidelines are presented to meet the ITRS projections. The design guidelines proposed for a 65 nm node are also examined for a 45 nm node for triple-and double-gate FinFETs. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimized to achieve low values of intrinsic delay. FinFETs should be designed with a higher aspect ratio (∼4) along with lower values of fin thickness to achieve ITRS targets for off-current and intrinsic delay. Triple-gate FinFETs show greater design flexibility in selecting important technological and device parameters as compared to double-gate devices. A design window is presented to achieve ITRS targets for the three logic technology requirements with triple-and double-gate FinFETs.

No abstract

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A VO ) and cutoff frequency (f T ) of 25-nm gate-length FinFETs operated at low drain-current (I ds = 10 µA/µm). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A VO (∼45 dB) and f T (∼70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.Index Terms-Cutoff frequency, early voltage, FinFETs, gate capacitances, intrinsic voltage gain, low-voltage/low-power analog applications, source/drain extension (SDE) region engineering, transconductance-to-current ratio.

No abstract

No abstract

No abstract

A new physical model based on two dimensional simulations for high quality laser re-crystallised poly-Si thin film transistors is presented. It has been shown that to adequately explain the improved subthreshold slope and the lack of saturation of the output characteristics in these transistors, it is essential to distribute the density of defect states between traps in the grains alongside traps localised at grain boundaries. A double exponential density of states has been extracted for thin film transistors (TFTs) annealed at different excimer laser energies, using the field effect conductance method. By splitting the density of states between grain traps and grain boundary traps good fits to the output characteristics have been achieved. Lack of saturation is shown to be due to decrease in potential barrier at grain boundaries with increase in drain bias. At high gate voltages, however, evidence of a self-heating effect similar to that observed in silicon-on-insulator (SOI) transistors is apparent.