How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

Kranti, Abhinav; Armstrong, G.A.

doi:10.1016/j.sse.2008.06.051

Cited by 9 publications

(6 citation statements)

References 34 publications

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“…front gate of 60 nm and back gate of 120 nm, achieves nearly the same f T OTA as that designed with a conventional non-underlap S/D design with o/L g = 0 (ideal DG MOSFET). As already demonstrated in our earlier work [52,53], underlap DG devices are highly tolerant to detrimental effects associated with misaligned/oversized back gate and therefore the analog performance metrics do not degrade significantly. The immunity of individual devices to back gate misalignment and oversize results in higher values of A VO OTA and f T OTA in an underlap channel OTA.…”

Section: Gate Misalignment/oversize Effectssupporting

confidence: 62%

“…Although an oversize back gate can control the channel potential in a more efficient manner than a misaligned gate, it introduces additional parasitic capacitance which is detrimental for the analog/RF performance. Previously, several authors [23,[51][52][53] have analyzed the influence of the misaligned and oversized back gate on individual devices with non-underlap [23,51] and underlap S/D profiles [52,53]. However, results for the influence of the misalignment/oversize back gate in analog circuits such as OTAs have not been investigated.…”

Section: Gate Misalignment/oversize Effectsmentioning

confidence: 99%

“…This is because f T OTA is degraded by the additional fringing capacitance caused by the oversized back gate [53]. The transconductance (g m ) and drain conductance (g ds ) values in an underlap S/D design are mainly governed by S/D extension regions and do not significantly depend on o/L g [53]. As a result, A VO OTA does not degrade significantly with o/L g .…”

Section: Gate Misalignment/oversize Effectsmentioning

confidence: 99%

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Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

Kranti¹,

Rashmi²,

Armstrong³

2009

Semicond. Sci. Technol.

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In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A VO OTA ) > 55 dB and unity gain frequency (f T OTA ) ∼ 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A VO OTA and three fold enhancement in f T OTA over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A VO OTA values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f T OTA values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A VO OTA and f T OTA highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/σ ) ratio of 3.2 and operated below a bias current (I BIAS ) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

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Section: Gate Misalignment/oversize Effectssupporting

confidence: 62%

Section: Gate Misalignment/oversize Effectsmentioning

confidence: 99%

Section: Gate Misalignment/oversize Effectsmentioning

confidence: 99%

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Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

Kranti¹,

Rashmi²,

Armstrong³

2009

Semicond. Sci. Technol.

Self Cite

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“…The approach also permits the shifting of back gate in totality with the assistance of the electron beam position accuracy. While misalignment has been investigated for the loss of controllability over the conduction channel [37,38] and its effect on analog performance [39,40], it also acts as an effective approach to activate impact ionisation at sub-bandgap supply voltages as discussed in subsequent paragraphs. As shown in figure 3(c), back gate misalignment results in a significant change in the distribution of the electric field within the semiconductor film.…”

Section: Resultsmentioning

confidence: 99%

Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors

Gupta

Kranti²

2016

Nanotechnology

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In this work, we examine the feasibility of triggering impact ionisation at sub-bandgap voltages through optimal utilisation of structural non-ideality induced electric field redistribution in the semiconductor film for an energy efficient steep switching junctionless (JL) transistor. While misalignment between front and back gates is often considered as a disadvantage due to loss of gate controllability, the work highlights its usefulness and applicability in nanoscale devices to engineer the electric field to enhance the product of current density (J) and electric field (E) and activate impact ionisation at sub-bandgap applied voltages. Results show that intentionally misaligned gates in silicon and germanium based JL devices exhibit an inclined conduction channel and achieve a nearly ideal value of steep subthreshold swing (∼ 1 mV decade) at room temperature. The work provides new viewpoints to realise energy efficient JL devices through the sharp increase of drain current from off-state to on-state achieved due to intentional misalignment between front and back gates.

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“…Kaneko et al [3] presented the FinFET (FinField-effect transistor) process integration technology including improved sidewall transfer process applicable to both fins and gates. Kranti and Armstrong [4] proposed a new scaling theory to model short However, critical dimension (CD) variations can significantly alter the drive strength of a transistor gate, thereby affecting the timing or possibly even the functionality of critical circuits. Kobayashi et al [5] investigated the parasitic resistance and capacitance relating to spacer region of FinFETs by changing shape of the spacer region.…”

Section: Introductionmentioning

confidence: 99%

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

Weng

2010

Microelectronics Reliability

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How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

Cited by 9 publications

References 34 publications

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

Impact of gate–source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

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