Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

Abstract

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG_S) and bottom gate shift to drain side (DG_D). At the same gate misalignment value, DG_S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG_D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG_S, with 20% gate misalignment length ( mis ) over gate length ( ), or mis = 20%, was faster than that of two-gate aligned DG-SOI.Index Terms-Double-gate (DG), gate-all-around transistor (GAT), gate misalignment, silicon-on-insulator (SOI), source/drain asymmetry.

Performance assessment of charge plasma based hetero‐structure VTFET biosensor for linearity enhancement

“…It is observed from profiles that current in CP‐FG‐VTFET is higher compared to CP‐SG‐VTFET and CP‐AS‐VTFET, specifically, over smaller biasing range 19 . It is featured with weakening of drain bias‐induced gate control over tunneling junction.…”

“…It is observed from profiles that current in CP-FG-VTFET is higher compared to CP-SG-VTFET and CP-AS-VTFET, specifically, over smaller biasing range. 19 It is featured with weakening of drain bias-induced gate control over tunneling junction. At high drain voltages, the CP-SG-VTFET has a higher current value than the CP-FG-VTFET because it has a larger drain-controlled BTBT.…”

“…When the left gate metal gets closer to the source region, the electric attributes change, influencing the number of holes inside the source region. That misalignment degrades the holes ratio within the source region 19,20 …”

“…In addition to this, it alters the electrical characteristics of the biosensor, including the drain current value, threshold voltage, and surface potential. In case of double-gated TFET biosensor [18][19][20] for providing some tolerance to the fabrication engineer, a study has been done on misalignment between left and right gates. In this paper, the effect of gate misalignment is investigated at source-channel junction using an underlap region.…”

Enhanced capacitance ratio and low minimum capacitance of varactor devices based on depletion-mode Ga-doped ZnO TFTs with a drain-offset structure

“…The lower µ FE can be attributed to an increase in the channel resistance caused by the offset region between the gate and drain contacts [30,31]. The poor on/off current ratio is due to the higher gate leakage current, which in turn could be due to the increase in the overlap length between the gate and source electrodes [32][33][34][35]. The sourceto-gate overlap length was 10 µm in the conventional TFTs, whereas it was 25 µm for drain-offset TFTs.…”