Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs

Pretet, J.; Ioannou, D.E.; Subba, N.; Cristoloveanu, S.; Maszara, W.; Raynaud, C.

doi:10.1016/s0038-1101(02)00147-8

Cited by 24 publications

(9 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This tri-layers channel based structure on 45nm channel length compared with HOI MOSFET developed by Khiangte et.al. Equal potential is applied on each gate having same work function so that equal depletion region is created in the tri-layered channel resulting in lowering of the electric field penetration with minimal short channel effects [12][13][14]. The doping dependence model Shockley Read Hall recombination [15 -17] and strain induces based piezo-restive model [18] are incorporated in device simulation to investigate strain effect on electron velocity and drift velocity of electrons in tri-layered channel.…”

Section: Device Structure and Simulationmentioning

confidence: 99%

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

2019

IJITEE

View full text Add to dashboard Cite

The down scaling of Meatal Oxide Semiconductor Field Effect transistor (MOSFET) devices nevertheless the most important and effective way for accomplishing high performance with low power adopted the miniaturization trend of channel length from the past, which is very aggressive. The double gate NanoFET with the incorporation of the strain Silicon technology is developed here on 45nm gate length comprises of tri-layered (s-Si/s-SiGe/s-Si) channel region with varied thicknesses. The induction of strain increases mobility of charge carriers. Two gates are deployed in bottom and up side of strained channel provides better control over the depletion region developed by applying same gate bias voltage. This newly developed double gate NanoFET on 45nm channel length provides 63% reduced subthreshold leakage current, and maximum electron drift velocity in strained channel.

show abstract

Section: Device Structure and Simulationmentioning

confidence: 99%

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

2019

IJITEE

View full text Add to dashboard Cite

show abstract

“…For large and small width devices, these non-uniformities have different proportions, which give rise to the width dependence of degradation. In particular, in a technology with shallow trench isolation (STI), the electric field at the trench edge is enhanced [17] which introduces more severe hot-carrier effects. Hot carrier injection into the edge may not affect the entire channel for the wider devices while narrower devices would naturally experience this effect to a greater degree [5].…”

Section: Saturation Of Mobility Degradationmentioning

confidence: 99%

Degradations of Threshold Voltage, Mobility, and Drain Current and the Dependence on Transistor Geometry For Stressing at 77 K and 300 K

Deptuch

Hoff

et al. 2014

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

Based on test results and a procedure which can isolate threshold voltage degradation and mobility degradation from the drain current degradation, we found that the log-log curves of mobility degradation show saturation with a change of slope from about 0.4 to smaller values at room temperature. Although both the mobility and threshold voltage degradations are more severe at 77 K than at 300 K for the same stress time, the temperature effect on the mobility degradation is larger than that on the threshold voltage degradation. In addition, the degradations of transistors with three different widths are compared after the stress tests at room and cryogenic temperatures, leading to the observation of degradation dependence on the transistor width. It is observed that the width dependence is more evident at 300 K and the temperature plays a more significant role on the degradation for larger width transistors.

show abstract

“…In general, the conventional 'narrow channel' effect in planar SOI MOSFETs degrades the carrier mobility, threshold voltage and subthreshold swing, and is more important in short transistors. It was explained by a more defective and thinner Si film on the transistor edges 10 .…”

Section: Short Channel Effectmentioning

confidence: 99%

“…The sidewalls have an inferior crystalline quality and presumably a lower lifetime than the planar interfaces 10 . As the fin width decreases, the overall contribution of sidewalls increases, therefore the effective carrier lifetime is decreased.…”

Section: Gate-induced Floating Body Effect (Gifbe)mentioning

confidence: 99%

Short Channel, Floating Body, and 3d Coupling Effects in Triple-Gate Mosfet

Lee

Cristoloveanu

et al. 2008

Int. J. Hi. Spe. Ele. Syst.

View full text Add to dashboard Cite

We have investigated the short-channel effect (SCE), floating-body effect, and three-dimensional coupling effect in triple-gate MOSFET with various fin widths, gate lengths and number of fins. It is found that the SCE of these devices is alleviated as the fin width shrinks and does not depend on the number of fins. The gate-induced floating-body effect (GIFBE) is visible even in fully depleted (FD) triple-gate transistors when the film-buried oxide (BOX) interface is swept from depletion to accumulation by the back-gate bias. The 3-D coupling effect in vertical, lateral, and longitudinal directions was investigated for different channel geometries. The biasing condition which enables the simultaneous activation of all channels and gives rise to volume inversion is discussed.

show abstract

Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs

Cited by 24 publications

References 9 publications

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

Modelling and Simulation of Tri-layered (s-Si/s-SiGe/s-Si) Channel Double Gate Nano FET

Degradations of Threshold Voltage, Mobility, and Drain Current and the Dependence on Transistor Geometry For Stressing at 77 K and 300 K

Short Channel, Floating Body, and 3d Coupling Effects in Triple-Gate Mosfet

Contact Info

Product

Resources

About