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A sigma-delta digital/analog converter implemented in 0.6-CMOS uses a 6-bit modulator together with a segmented noise-shaped scrambling scheme to achieve 113-dB A-weighted dynamic range over a 20-kHz bandwidth. A continuous-time output stage is used to achieve high signal-to-noise ratio in a 9.1-mm 2 die area. The output stage uses a dual return-to-zero circuit that eliminates errors caused by intersymbol interference.

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Nanodiscs provide an excellent system for the structure-function investigation of membrane proteins. Its direct advantage lies in presenting a water-soluble form of an otherwise hydrophobic molecule, making it amenable to a plethora of solution techniques. Nuclear magnetic resonance is one such high-resolution approach that looks at the structure and dynamics of a protein with atomic level precision. Recently, there has been a breakthrough in making nanodiscs more susceptible for structure determination by solution NMR, yet it still remains to become the preferred choice for a membrane mimetic. In this practical review, we provide a general discourse on nanodisc and its application to solution NMR. We also offer potential solutions to remediate the technical challenges associated with nanodisc preparation and the choice of proper experimental set-ups. Along with discussing several structural applications, we demonstrate an alternative use of nanodiscs for functional studies, where we investigated the phosphorylation of a cell surface receptor, integrin. This is the first successful manifestation of observing activated receptor phosphorylation in nanodisc through NMR. We additionally present an on-column method for nanodisc preparation with multiple strategies and discuss the potential use of alternative nanoscale phospholipid bilayer systems like styrene maleic acid lipid disc and saposin-A lipoprotein disc.Keywords: beta barrel; integrin; membrane proteins; nanodisc; nanoscale phospholipid bilayers; saposin-A; SMALP; solution NMR; styrene maleic acid; transmembrane Users without a subscription are not able to see the full content. Please, subscribe or login to access all content.

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Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low power consumption such that the system can be housed in a small low-cost plastic package. Several 120dB SNR audio ΔΣ DACs have been reported using either switched-capacitor or continuous-time techniques [1][2][3]. This paper presents a continuous time (CT) area-optimized multibit DAC which achieves 120dB SNR and 100dB THD+N at 21.5mW/channel. This performance is achieved by using a new 3-level rotational data shuffling scheme which achieves small area and low digital activity at low signal level, and by applying low-power low-noise analog techniques.Assuming a thermal resistance of 42.3°C/W (typical low-cost LQFP) and a maximum junction temperature of 150°C, a 16 channel DAC would need to have a power consumption of less than 36.9mW/channel for an operational temperature of 125°C. This limit is more stringent than that of any of the previously reported high-end DACs [1-3]. High performance and low power are enabled in the present design by using both architectural-and circuit-level considerations. The first architecture-level consideration is choosing a CT approach so that the analog section of the DAC is less prone to pick up on-chip digital noise. Second, a 2 nd -order 8b modulator is used to reduce clock jitter requirements and to achieve low out-of-band noise. Third, a 3-level rotational dynamic element matching (DEM) scheme is introduced which achieves better SNR performance and lower power consumption than that of previously presented work [4]. Fourth, a signed-magnitude approach is taken at the boundary between the digital and the analog domains such that combined with the 3-level rotational DEM technique would ensure the digital activities at the boundary are proportional to the input signal amplitude which reduces digital coupling effects at low input levels. This approach would also reduce the operational power. At the circuit level the key considerations are the power, noise, and area tradeoffs of the DAC output stage, design of the 3-level current sources (I-DACs) for reduced elementto-element mismatch, and of low-noise voltage reference generators. Figure 27.7.1 shows the block diagram of one channel of the DAC. Digital audio is received at the input by a serial audio interface capable of receiving all standard audio formats. The signal is then passed to a 4× interpolation filter that uses canonical signed-digit arithmetic for low power consumption. The filter also performs volume control and de-emphasis functions. The filter engine output is then further interpolated to 128× via a linear interpolation, and is then presented to the 2 nd -order 8b modulator. For area and power considerations a noise-shaped segmentation technique is used, to split the 8b modulator data into a 4b word with a weight of 16×, and a pair of 3b words with weights of 4× and 1×, respectively. The gain errors between the weighted segments are 1...