A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling

Adams, Robert; Nguyen, Khiem; Sweetland, Karl

doi:10.1109/isscc.1998.672376

Cited by 35 publications

(22 citation statements)

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“…Return-to-zero [4,6,19,20,24,26] hardware level Switching using return-to-zero can reduce timing errors and suppress signaldependent phenomena. Medium Medium Differential current switches [19,26,27] hardware level…”

Section: Medium Mediummentioning

confidence: 99%

Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters

Eielsen

Leth

Fleming

et al. 2020

IEEE Trans. Signal Process.

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Glitches introduce impulse-like disturbances which are not be readily attenuated by low-pass filtering. This article presents a model that describes the behaviour of glitches, and a method for mitigation based on a large-amplitude dither signal. Analytical and experimental results demonstrate that a dither signal with sufficient amplitude can mitigate the effect of glitches, when used in conjunction with a low-pass filter. The dither signal in conjunction with low-pass filtering essentially converts a glitch from a high-frequency to low-frequency disturbance.

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Section: Medium Mediummentioning

confidence: 99%

Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters

Eielsen

Leth

Fleming

et al. 2020

IEEE Trans. Signal Process.

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“…The frequency of the CHS is set at half the sampling frequency (Fs/2). The RZ scheme has another benefit, which is the elimination of intersymbol interference (ISI) errors [13]. A folded cascode OTA is used as an amplifier thanks to the feed-forward path.…”

Section: Chs In Continuous-time Integratormentioning

confidence: 99%

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Kim¹

2011

ETRI J

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A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital-toanalog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm 2 . The ΔΣ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns RMS external clock jitter.

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“…This forces to face a trade-o between single-ended (SE) and fully di erential (FD) analog signal processing blocks. In fact the required high-performances for audio applications are typically obtained by using FD solutions (for instance, SC ÿlters [1], and mainly to A-to-D [2,3] and D-to-A [4][5][6][7] oversampled converters have been reported).…”

Section: Introductionmentioning

confidence: 99%

90dB‐DR 3.3V CMOS single‐ended‐to‐fully differential and fully differential‐to‐single‐ended amplifiers for audio applications

Boarin

Colonna

Gandolfi

et al. 2003

Circuit Theory & Apps

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SUMMARYThis paper presents the design and the realization of single-ended-to-fully di erential and fully di erential-to-single-ended ampliÿers to be used in an audio signal processing system. The proposed blocks allow to reduce signiÿcantly the pin number of the developed system, while guaranteeing the high quality (16 bit) performance required in an audio channel. The proposed circuits have been realized in a standard 3:3 V 0:35 m CMOS technology and achieve a Dynamic Range in excess of 90 dB with a Total Harmonic Distortion lower than −80 dB for a full scale signal amplitude. Their power consumption (≈ 6 mW and each) and the area (0:1 mm 2 each) are ÿnally negligible with respect to the other blocks in the overall systems.

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A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling

Cited by 35 publications

References 0 publications

Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters

Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

90dB‐DR 3.3V CMOS single‐ended‐to‐fully differential and fully differential‐to‐single‐ended amplifiers for audio applications

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