A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

Nguyen, Khiem; Adams, Robert; Sweetland, Karl; Chen, Huaijin

doi:10.1109/jssc.2005.856284

Cited by 83 publications

(55 citation statements)

References 6 publications

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“…Table 3 compares the simulated performance of the presented FDSOI design with several continuous-time ΔΣ ADCs from recent literature [7,[18][19][20][21][22]. The chip was wire-bonded in a DIP package, mounted on a PCB and tested.…”

Section: Simulation Resultsmentioning

confidence: 99%

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

Balagopal

Saxena

2012

JLPEA

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A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level.

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Section: Simulation Resultsmentioning

confidence: 99%

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

Balagopal

Saxena

2012

JLPEA

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“…The coefficient variation of the first integrator can lead to degradation in the performance of the ΔΣ modulator [1]. Therefore, it is important to calibrate the coefficient of the CT integrator to prevent the performance degradation or the modulator from becoming unstable.…”

Section: Dac Pulse Generatormentioning

confidence: 99%

“…To avoid these drawbacks of a DT ΔΣ modulator, hybrid ΔΣ modulators composed of continuous-time (CT) and DT integrators have been reported in [1]- [4]. Compared to a ΔΣ modulator consisting of only DT integrators, a hybrid ΔΣ modulator offers several important advantages.…”

Section: Introductionmentioning

confidence: 99%

“…This feed-forward path makes the first integrator process a second-order high-pass filtered signal component, thereby reducing the signal swing at the first integrator output and saving power consumption [7]- [9]. A feed-forward path could be implemented using a different method that connects the input of the ΔΣ modulator to the input of the second integrator, as in [1]. This method creates the same effect as the previous one.…”

Section: Introductionmentioning

confidence: 99%

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A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Kim¹

2011

ETRI J

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A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital-toanalog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm 2 . The ΔΣ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns RMS external clock jitter.

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“…Recent audio CODECs for digital TVs and mobile phones are required to have multiple channels since audio applications for these systems may need to process various media sources and multiple concurrent user functions at the same time [1]. These channels may be operated with separate independent clocks coming from different clock sources for different applications.…”

Section: Introductionmentioning

confidence: 99%

Multi-Channel Audio CODEC with Channel Interference Suppression

Choi¹,

Lee

Lee³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A multi-channel audio CODEC with interchannel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.

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A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

Cited by 83 publications

References 6 publications

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Multi-Channel Audio CODEC with Channel Interference Suppression

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