Nano-scale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired. This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18μm CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses, and demonstrate an in-situ associative learning. The neuron circuit occupies a small area of 0.01mm 2 and has an energy-efficiency of 9.3pJ/spike/synapse. 1
A third-order single-bit CTmodulator for generic biomedical applications is implemented in a 0.15-μm FD-SOI CMOS process. The overall power efficiency is attained by employing a single-bit quantizer and thus avoiding the mismatch shaping logic. The loop filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CTmodulator consumes 110μW power from a 1.5-V power supply when clocked at 6.144MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) of this third-order, single-bit CTmodulator is 0.271pJ/level.
A 1 GS/s Continuous-time Delta-Sigma modulator (CT-∆ΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB signal-to-noise is reported in a 0.13 µm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT-∆Σ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT-∆ΣM has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.
Index Terms-Analog-digital (A/D) conversion, continuoustime (CT), delta-sigma (△Σ), excess loop delay (ELD), feedforward, signal transfer function (STF).
Abstract-A design methodology for synthesizing poweroptimized decimation filters for wideband Delta Sigma ( Σ ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuoustime Σ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45nm CMOS technology occupies a layout area of 0.12 mm 2 and consumes 8 mW power from the 1.1V supply.
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