Abstract-A design methodology for synthesizing poweroptimized decimation filters for wideband Delta Sigma ( Σ ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuoustime Σ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45nm CMOS technology occupies a layout area of 0.12 mm 2 and consumes 8 mW power from the 1.1V supply.
Abstract-The design considerations for low-power continuoustime (CT) delta-sigma (∆Σ) modulators is studied and circuit design details for a 13.5 bit modulator are given. The converter has been designed in a 0.5 um C5FN AMI CMOS technology and achieves a maximum signal-to-noise ratio (SN R) of 85 dB in a 48 kHz bandwidth and dissipates 5.4 mW from a 5 V supply when clocked at 6.144 M Hz. It features a third-order active-RC loop filter, a 4-bit flash quantizer along with a Data Weighted averaging (DWA). The loop filter architecture and its coefficients have been targeted for the minimum power dissipation. The DWA also has been implemented by standard cell based synthesis to further optimize power. The figure of merit (F oM ) of the CT-∆Σ modulator is 3.71 pJ/bit. The fabricated chip of the modulator occupies an area of 4.5 mm 2 .
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