A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and <italic>In Situ</italic> Learning

Abstract

Nano-scale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired. This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18μm CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses, and demonstrate an in-situ associative learning. The neuron circuit occupies a small area of 0.01mm 2 and has an energy-efficiency of 9.3pJ/spike/synapse. 1

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip

“…By comparing with the contemporary advanced GPU Nvidia P4 [24] (170 images/s/W), a memristive architecture with R LRS = 100kΩ provides a meagre 14× improvement in energy-efficiency. However, the energy consumption can be significantly reduced if the LRS resistance of the memristive devices can be increased to high-M Ω regime, leading to a potential 1000× range performance improvement; high LRS also helps reduce the power consumption in the opamp-based neuron circuits [22], [25].Since there has been less focus on realizing high-LRS devices as the multi-valued memristive devices are still under development, circuit solutions are desired to address this wide energy-efficiency gap.…”

“…Memristive spiking circuits typically use analog spikes with rectangular positive pulse with a negative exponential tail [22]; however, representation of spikes with digital pulses is highly desirable for large-scale NeuSoC implementation. Further, an accelerated neural dynamics with moderate speed (few MHz's) is preferred over biological time-scales (sub-kHz) for optimizing CMOS circuit area and energy consumption [36].…”

“…The memristive synapse, for the given sizing for M 1 , realizes LRS and HRS resistances of 0.4M Ω and 16M Ω respectively, providing significant improvement over contemporary memristive devices. As detailed in [22], [30], the traditional subthreshold neuron designs are not suitable for driving memristive load. The opamp-based integrate-andfire neurons with winner-take-all STDP learning interface from author's prior work in [30] can directly be adapted to interface with the presented synapses; higher LRS resistance will further help simply opamp design.…”

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

“…Traditional von Neumann computing systems based on CMOS technologies cannot achieve this level of energy efficiency. Neuromorphic hardware systems that potentially provide the capabilities of biological perception and information processing have gained much attention [75,76]. Bio-inspired neuromorphic computing may open a door to novel computation and communication paradigms.…”

Dendritic-Inspired Processing Enables Bio-Plausible STDP in Compound Binary Synapses

“…Further, these devices have shown low-energy consumption to change their states and very compact layout footprint [4]- [9]. Hybrid CMOS-RRAM analog very-largescale integrated (VLSI) circuits have been proposed [10], [11] [20,21] to achieve dense integration of CMOS neurons and emerging devices for neuromorphic system-on-a-chip (NeuSoC). Fig.1a illustrates a NeuSoC architecture where a three layer fully-connected spiking neural network is envisioned.…”