A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique

Nguyen, Khiem; Bandyopadhyay, Abhishek; Adams, Bob; Sweetland, Karl; Baginski, P.

doi:10.1109/isscc.2008.4523270

Cited by 23 publications

(6 citation statements)

References 3 publications

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“…Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g., segmenting [1] or cascading [2]. Unlike 1b modulation, the multi-level DACs need mismatch shaping algorithms to compensate for the typical 0.1 to 1% on-die mismatch.…”

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confidence: 99%

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A 108dB-DR 120dB-THD and 0.5V<inf>rms</inf> output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS

Risbo

Hezar

Kelleci

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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The current trend in high-performance audio DACs is to use fine-resolution quantization to reduce the out-of-band noise (OBN), reduce jitter sensitivity, and simplify analog filtering. Recent techniques achieve this goal by using a mix of DAC elements with different weights, e.g., segmenting [1] or cascading [2]. Unlike 1b modulation, the multi-level DACs need mismatch shaping algorithms to compensate for the typical 0.1 to 1% on-die mismatch. In addition to the element mismatch, dynamic error sources such as asymmetrical switching, clock skew, and parasitic memory are major hindrances to achieve distortion and dynamic range targets. The resulting dependence of present symbol error to the past symbol is referred to as inter-symbol-interference (ISI), and is a function of the switching activity of all the individual DAC elements. Unfortunately, the popular mismatch-shaping algorithms (e.g., rotation-DWA) are addressing only the static mismatch problem. They typically increase the switching activity thus amplify ISI errors. Furthermore, the error comes often in the form of spurious tones with signal-dependent frequency (FM modulation [3]) that ruins the lowamplitude performance (harmonics for a -60dB signal) which is critical for the perceived sound quality. A common remedy is to add a digital DC offset to shift the tones out of band. However, this merely moves the problematic amplitude region, and does not solve the problem. Moreover, ISI errors often limit the large signal THD as a result of a strong signal-dependent modulation of the element transition rate.One popular analog solution to reduce ISI errors is to use return-to-zero (RTZ) which eliminates the dependence on previous symbol. However, it results in increased current consumption, more high-frequency components, and higher sensitivity to circuit timing/jitter. Another analog solution [1] is to use a trackand-hold circuit to deglitch the waveform. However, such sampling circuits are sensitive to aliasing of high-frequency noise. Other proposed techniques [4] use modified digital algorithms with various trade-offs between mismatch shaping and the element transition rate. The pulse-width modulation (PWM) DAC method in [2] forces a fixed transition rate of the DAC elements, resulting in a significantly reduced sensitivity to ISI. However, this comes at the expense of a high clock rate which may not be available in the system.We propose a new digital algorithm that can shape element mismatch and ISI errors simultaneously. This method fully shapes ISI and the mismatch errors outside audio band and eliminates the need for layout critical and non-automated analog design methods that often require multiple design iterations and are hard to migrate over processes. This is enabled by using digital processing circuits that are simple and predictable with modern EDA tools and come at low cost in power and area using deep-submicron CMOS. In addition, the proposed solution works at regular DSM clock rate and does not require another PLL and clock management circuit.Th...

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confidence: 99%

“…However, it results in increased current consumption, more high-frequency components, and higher sensitivity to circuit timing/jitter. Another analog solution [1] is to use a trackand-hold circuit to deglitch the waveform. However, such sampling circuits are sensitive to aliasing of high-frequency noise.…”

mentioning

confidence: 99%

A 108dB-DR 120dB-THD and 0.5V<inf>rms</inf> output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS

Risbo

Hezar

Kelleci

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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“…Second, a 2 nd -order 8b modulator is used to reduce clock jitter requirements and to achieve low out-of-band noise. Third, a 3-level rotational dynamic element matching (DEM) scheme is introduced which achieves better SNR performance and lower power consumption than that of previously presented work [4]. Fourth, a signed-magnitude approach is taken at the boundary between the digital and the analog domains such that combined with the 3-level rotational DEM technique would ensure the digital activities at the boundary are proportional to the input signal amplitude which reduces digital coupling effects at low input levels.…”

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confidence: 99%

“…For area and power considerations a noise-shaped segmentation technique is used, to split the 8b modulator data into a 4b word with a weight of 16×, and a pair of 3b words with weights of 4× and 1×, respectively. The gain errors between the weighted segments are 1 st -order noise shaped [4]. After a sign-magnitude thermometer code conversion individual rotational shuffling is applied to each of the segmented data.…”

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confidence: 99%

“…The currents are generated from low-noise reference generators. A clock generator generates the required signals for the ISI-free operation of the output stage [4]. It can be seen that since the pointers advance in the same direction and wrap around, over time, all elements will be used equally thereby ensuring that the long term average errors contributed by each element approach zero.…”

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A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC

Bandyopadhyay

Determan

Kim

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low power consumption such that the system can be housed in a small low-cost plastic package. Several 120dB SNR audio ΔΣ DACs have been reported using either switched-capacitor or continuous-time techniques [1][2][3]. This paper presents a continuous time (CT) area-optimized multibit DAC which achieves 120dB SNR and 100dB THD+N at 21.5mW/channel. This performance is achieved by using a new 3-level rotational data shuffling scheme which achieves small area and low digital activity at low signal level, and by applying low-power low-noise analog techniques.Assuming a thermal resistance of 42.3°C/W (typical low-cost LQFP) and a maximum junction temperature of 150°C, a 16 channel DAC would need to have a power consumption of less than 36.9mW/channel for an operational temperature of 125°C. This limit is more stringent than that of any of the previously reported high-end DACs [1-3]. High performance and low power are enabled in the present design by using both architectural-and circuit-level considerations. The first architecture-level consideration is choosing a CT approach so that the analog section of the DAC is less prone to pick up on-chip digital noise. Second, a 2 nd -order 8b modulator is used to reduce clock jitter requirements and to achieve low out-of-band noise. Third, a 3-level rotational dynamic element matching (DEM) scheme is introduced which achieves better SNR performance and lower power consumption than that of previously presented work [4]. Fourth, a signed-magnitude approach is taken at the boundary between the digital and the analog domains such that combined with the 3-level rotational DEM technique would ensure the digital activities at the boundary are proportional to the input signal amplitude which reduces digital coupling effects at low input levels. This approach would also reduce the operational power. At the circuit level the key considerations are the power, noise, and area tradeoffs of the DAC output stage, design of the 3-level current sources (I-DACs) for reduced elementto-element mismatch, and of low-noise voltage reference generators. Figure 27.7.1 shows the block diagram of one channel of the DAC. Digital audio is received at the input by a serial audio interface capable of receiving all standard audio formats. The signal is then passed to a 4× interpolation filter that uses canonical signed-digit arithmetic for low power consumption. The filter also performs volume control and de-emphasis functions. The filter engine output is then further interpolated to 128× via a linear interpolation, and is then presented to the 2 nd -order 8b modulator. For area and power considerations a noise-shaped segmentation technique is used, to split the 8b modulator data into a 4b word with a weight of 16×, and a pair of 3b words with weights of 4× and 1×, respectively. The gain errors between the weighted segments are 1...

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