A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC

Abstract

Automotive and consumer multi-channel 24b audio systems have demanded low-cost digital-to-analog converters (DACs) which offer wide dynamic range, high linearity, small die size, and low power consumption such that the system can be housed in a small low-cost plastic package. Several 120dB SNR audio ΔΣ DACs have been reported using either switched-capacitor or continuous-time techniques [1][2][3]. This paper presents a continuous time (CT) area-optimized multibit DAC which achieves 120dB SNR and 100dB THD+N at 21.5mW/channel. This performance is achieved by using a new 3-level rotational data shuffling scheme which achieves small area and low digital activity at low signal level, and by applying low-power low-noise analog techniques.Assuming a thermal resistance of 42.3°C/W (typical low-cost LQFP) and a maximum junction temperature of 150°C, a 16 channel DAC would need to have a power consumption of less than 36.9mW/channel for an operational temperature of 125°C. This limit is more stringent than that of any of the previously reported high-end DACs [1-3]. High performance and low power are enabled in the present design by using both architectural-and circuit-level considerations. The first architecture-level consideration is choosing a CT approach so that the analog section of the DAC is less prone to pick up on-chip digital noise. Second, a 2 nd -order 8b modulator is used to reduce clock jitter requirements and to achieve low out-of-band noise. Third, a 3-level rotational dynamic element matching (DEM) scheme is introduced which achieves better SNR performance and lower power consumption than that of previously presented work [4]. Fourth, a signed-magnitude approach is taken at the boundary between the digital and the analog domains such that combined with the 3-level rotational DEM technique would ensure the digital activities at the boundary are proportional to the input signal amplitude which reduces digital coupling effects at low input levels. This approach would also reduce the operational power. At the circuit level the key considerations are the power, noise, and area tradeoffs of the DAC output stage, design of the 3-level current sources (I-DACs) for reduced elementto-element mismatch, and of low-noise voltage reference generators. Figure 27.7.1 shows the block diagram of one channel of the DAC. Digital audio is received at the input by a serial audio interface capable of receiving all standard audio formats. The signal is then passed to a 4× interpolation filter that uses canonical signed-digit arithmetic for low power consumption. The filter also performs volume control and de-emphasis functions. The filter engine output is then further interpolated to 128× via a linear interpolation, and is then presented to the 2 nd -order 8b modulator. For area and power considerations a noise-shaped segmentation technique is used, to split the 8b modulator data into a 4b word with a weight of 16×, and a pair of 3b words with weights of 4× and 1×, respectively. The gain errors between the weighted segments are 1...

Class D Amplifiers (CDAs) : PWM-in-PWM-out CDA, Filterless Bang-Bang CDA, and high-frequency high-efficiency CDA for Envelope Tracking

“…Interestingly, the Class D Amplifier (CDA) is a common circuit block as an audio amplifier and an amplifier to provide the varying supply voltage to the RF PA [2,[4][5][6][7][8][9][10][11]. In addition to power-efficiency considerations [12][13][14], contemporary audio-related electronic devices are also expected to feature high quality audio, if possible to high-fidelity standards [15] (e.g., qualified by Total Harmonic Distortion, THD [14,[16][17][18][19][20][21][22]), and in the presence of circuit noise (qualified by Power Supply Rejection Ratio, PSRR [19,21,[23][24][25][26][27]).…”

“…Of the various non-linearities, THD [14,[17][18][19][20][21][22] is arguably of the greatest interest because THD is typically quoted and generally easily perceived psycho-acoustically.…”

“…Second, in a mobile device where many modules are likely to be integrated into an SoC, noise (include ground-bounce noise or power supply noise induced by both audio power amplifiers and radio frequency power amplifiers) can easily couple to the DAC via the substrate and/or the supply rails. This drastically undermining the performance of the DAC [18].…”

Analysis and design of audio class D amplifiers

“…THD+N of the order of 0.002%[49,86,87]. To ensure that these smart devices retain their overall (system) audio fidelity, the audio amplifier embodied therein would likewise need to feature commensurable high fidelity, including THD+N of the same order.…”