A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling

Adams, Robert; Nguyen, Khiem; Sweetland, Karl

doi:10.1109/4.735526

Cited by 133 publications

(31 citation statements)

References 4 publications

(8 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The frequency of the CHS is set at half the sampling frequency (Fs/2). The RZ scheme has another benefit, which is the elimination of intersymbol interference (ISI) errors [13]. A folded cascode OTA is used as an amplifier thanks to the feed-forward path.…”

Section: Chs In Continuous-time Integratormentioning

confidence: 99%

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Kim¹

2011

ETRI J

View full text Add to dashboard Cite

A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital-toanalog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm 2 . The ΔΣ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns RMS external clock jitter.

show abstract

Section: Chs In Continuous-time Integratormentioning

confidence: 99%

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Kim¹

2011

ETRI J

View full text Add to dashboard Cite

show abstract

“…This way, some kind of linearization scheme is needed if a linearity beyond the intrinsic device matching is required. For this purpose, dynamic element matching techniques, which achieve spectral shaping of the DAC errors, have been successfully exploited [1][2][3][4][5][6][7][8][9]. However, at low oversampling ratios, such dynamic element matching techniques become inefficient and calibration techniques come into the picture [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Calibration of DAC Mismatch Errors in $\Sigma\Delta$ ADCs Based on a Sine-Wave Measurement

Bock

Xing

Weyten

et al. 2013

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

Abstract-We present an off-line calibration procedure to correct the non-linearity due to DAC mismatch in multi-bit Σ∆-modulation A/Dconverters. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC-errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method it may also be a viable approach for factory calibration.

show abstract

“…The DEM method has been used by many researchers to improve the performance of DACs [6][7][8][9][10]. Most researchers use these DACs on Delta-Sigma converters when high linearity is required.…”

Section: Introductionmentioning

confidence: 99%

Testing high resolution ADCs using deterministic dynamic element matching

Olleta

Jiang

Chen

et al.

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

View full text Add to dashboard Cite

Dynamic element matching (DEM) is an effective approach to achieving good average performance in the presence of major mismatch in matching-critical circuits. This paper presents a deterministic DEM (DDEM) strategy for ADC testing that offers substantial reductions in testing cost.The approach is mathematically formulated and validated with simulation results that show the number of test vectors needed is comparable to what are currently used with standard code density linearity testing. It is demonstrated that the DDEM method can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique offers potential for use in both production test and BIST environments where high linearity devices are difficult to test and characterize.

show abstract

A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling

Cited by 133 publications

References 4 publications

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

A Hybrid Audio ΔΣ Modulator with dB-Linear Gain Control Function

Calibration of DAC Mismatch Errors in $\Sigma\Delta$ ADCs Based on a Sine-Wave Measurement

Testing high resolution ADCs using deterministic dynamic element matching

Contact Info

Product

Resources

About