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This work presents a novel energy conservation technique based on predicting the load current of a DC-DC converter that may feed a variety of loads, such as speakers and displays. The predicted load cnrrent is used to dynamically adjust the size of the output stage transistors and to switch into PFM mode to maximize the instantaneous converter efficiency. By using a segmented output stage, the trade-off between the gate drive losses and RMS conduction losses can be continuously optimized over the full load current range. The technique relies on the fact that the digital data stream which feeds modern electronic loads can be processed in real-time to predict the load cnrrent without relying on explicit cnrrent sensing or slow steady-state calibration techniques. The experimental prototype includes a digitally controlled 3.6V-to-L.8V DC-DC converter with an integrated segmented power stage IC operating at 4 MHz. A high-fidelity class-D audio amplifier acts as the DC-DC converter load. The results show a good agreement between the digitally predicted and actual DC-DC converter load current. The total energy consumed for three music pieces was reduced by up to 38% using the automatic mode/segment control technique. The fully digital efficiency optimization technique is well suited to future monolithic integration in advanced CMOS processes.

Abstract-A new capacitor and opamp sharing technique that enables a very efficient low power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back in the absence of sample and hold is also presented. Fabricated in a 0.18-µm CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm of active die area and achieves 66.7dB SFDR and 53.2dB SNDR when a 1MHz input signal is digitized at 80MS/s. The SFDR and SNDR are unchanged for 50MHz input signal. The prototype ADC consumes 36mW at 1.8V supply, of which analog portion consumes 24mW. 2

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