A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$98 dB THD, and 79 dB SNDR

Lee, Kyehyung; Chae, Jeongseok; Aniya, M.; Hamashita, Koichi; Takasuka, K.; Takeuchi, Shigeyuki; Temes, Gábor C.

doi:10.1109/jssc.2008.2006311

Cited by 55 publications

(20 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…18 This proposed structure combines the efficiency of a pipelined ADC with the noise shaping property of a singleloop delta-sigma modulator. The figure-of-merit [13] of this modulator is among the best reported for high bandwidth switch-capacitor (SC) delta-sigma ADCs. Although there are some SC delta-sigma modulators with better FOMs [13], the HDSP modulator shows the best FOM at low OSRs.…”

Section: Measurement Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Rajaee

Musah

Maghari

et al. 2010

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.

show abstract

Section: Measurement Resultsmentioning

confidence: 99%

“…Equation (13) shows that errors generated by the first pipelined stage are shaped by the loop filter . This will greatly relax the design requirements of the first pipelined stage.…”

Section: The Pipelined Adcmentioning

confidence: 99%

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Rajaee

Musah

Maghari

et al. 2010

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

show abstract

“…But a modulator with higher order loop filter will also result in more power dissipation by adding more active blocks. As an alternate solution, the noise-coupling technique was introduced by [3,4] to enhance quantization noise shaping in ΔΣ modulators without adding any active circuit blocks. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A new zero-optimization scheme for noise-coupled ΔΣ ADCs

Zanbaghi

Fiez

Temes

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

This paper presents a new zero-optimization scheme for noise-coupled ΔΣ analog-to-digital converters (ADCs). The proposed technique enhances the signal-toquantization-noise-ratio (SQNR) by optimizing noise-transferfunction (NTF) zero locations to get maximum in-band noise shaping. The amount of SQNR improvement using the new scheme depends on the order of the modulator. Therefore, zero optimization will be used in a first-order and a second-order modified noise-coupled ΔΣ ADCs. The proposed technique enhances the SQNR of the first-order and second-order noisecoupled ΔΣ modulators by 4.5dB and 8.5 dB, respectively.

show abstract

“…inter-channel coupling gain. Although similar in nature, it is of critical importance to distinguish between the proposed technique and the noise-coupled time-interleaved modulators [3] where noise-coupling is employed to result in an extra zero in the band without modifying the rest of the NTF zero placements. The traditional path coupling technique also requires extra DACs to extract the quantisation error to realise the required coupling coefficients in order to achieve higher order of noise shaping, thus having a significant thermal noise contribution.…”

mentioning

confidence: 99%

Time-interleaved noise-shaping integrating quantisers

Maghari

Musah

et al. 2010

Electron. Lett.

View full text Add to dashboard Cite

A new time-interleaved noise-shaping quantiser architecture is proposed. By employing a time-interleaving technique with a new path-coupling scheme, higher order of noise shaping and increased bandwidth are achieved. This general topology can be employed to synthesise any noise transfer function without the need for dedicated digital-to-analogue converters to extract the quantisation noise. Simulation results are provided to verify the effectiveness of this structure.Introduction: Single-slope and dual-slope analogue-to-digital converters (ADCs) are known for high linearity and guaranteed monotonicity, but they are slow in nature. A similarly natured integrating quantiser based on modified discharging phase [1] could introduce a first-order quantisation noise-shaping. Despite the advantageous quantisation noise-shaping, these structures are still limited to low-to-medium bandwidth.To increase the effective bandwidth of these ADCs, an approach based on time-interleaving of multiple channels of the integrating quantisers is presented. In addition, to employ more aggressive quantisation noise-shaping, time-based quantisation noise-coupling is proposed. Hence not only is the effective sampling rate is increased, but also a higher order of noise shaping is achieved.

show abstract

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$98 dB THD, and 79 dB SNDR

Cited by 55 publications

References 21 publications

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

A new zero-optimization scheme for noise-coupled ΔΣ ADCs

Time-interleaved noise-shaping integrating quantisers

Contact Info

Product

Resources

About

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$98 dB THD, and 79 dB SNDR

Cited by 55 publications

References 21 publications

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

A new zero-optimization scheme for noise-coupled &#x0394;&#x03A3; ADCs

Time-interleaved noise-shaping integrating quantisers

Contact Info

Product

Resources

About

A new zero-optimization scheme for noise-coupled ΔΣ ADCs