Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Abstract

A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.

Low-power sigma-delta modulator with half-sample delayed-input feedforward

“…To relax the timing requirements imposed on the modulator feedback loop, a onesample or half-sample delay can be inserted into forward and feedback path [2,3], as shown in Fig. 1.…”

A 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS

“…Although flash ADCs are the common architecture to realize the quantizer, they require many comparators and a relatively large encoder, complicating the design of the quantizer. Alternatively, a two-step ADC quantizer is a good candidate to increase the quantizer's resolution without requiring many comparators and a large digital encoder (e.g., [12,13] in discrete-time modulators). Thus, in this work, a multi-bit two-step-ADC quantizer, along with a foreground digital binary-DAC calibration technique, is introduced within the continuous-time delta-sigma modulator.…”

A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End

“…Flash ADCs [36] achieve high sampling rates at low resolution (usually bits), pipeline ADCs [38], [44], [47] can achieve resolution bits when calibrated at a sampling rate up to few hundred MS/s, and successive approximation register architecture (SAR) [37], [45] and sigma-delta ADCs [39], [42], [46] can achieve high resolution ( bits) at limited effective signal bandwidths up to around 100 MHz without time-interleaving. However, an ADC with both high resolution and high sampling rate is difficult to design for systems where power consumption is a significant constraint.…”