A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing

Sasidhar, N.; Kook, Youn-Jae; Takeuchi, Shigeyuki; Hamashita, Koichi; Takasuka, K.; Hanumolu, Pavan Kumar; Moon, Un-Ku

doi:10.1109/asscc.2007.4425775

Cited by 10 publications

(9 citation statements)

References 6 publications

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“…14. The third stage shares an amplifier with the second pipelined stage [7]. The two local feedback paths from the output of the third stage to the input of the second pipelined stage are also shown in this figure.…”

Section: B Pipelined Adc Circuit Implementationmentioning

confidence: 96%

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Rajaee

Musah

Maghari

et al. 2010

IEEE J. Solid-State Circuits

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A hybrid delta-sigma/pipelined modulator is presented in this paper. The proposed modulator takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta-sigma modulator. As a result, gain, swing, and slew requirements of the integrators are significantly reduced. The modulator also makes use of the latency in the pipelined quantization to enhance noise shaping. These advantages lead to less power dissipation, increased stability, and higher resolution. The prototype chip is implemented in a 0.18 m CMOS process. With an 80 MHz clock, and an oversampling ratio of 8 (5 MHz bandwidth), the measured dynamic range and SNDR of this prototype IC are 79 dB and 75.4 dB.

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Section: B Pipelined Adc Circuit Implementationmentioning

confidence: 96%

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Rajaee

Musah

Maghari

et al. 2010

IEEE J. Solid-State Circuits

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show abstract

“…However, with capacitor-sharing, the scaling factor between the first and second stages is 0.5. This increases the input-referred noise by about 27% (a detailed explanation can be found in [17]). To compensate for the extra noise, one can increase the capacitor sizes in the first or second or both stages of the pipeline.…”

Section: Effect Of Capacitor-sharing On Noisementioning

confidence: 97%

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

Lee

Tsang

2009

IEEE J. Solid-State Circuits

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A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variableopamp. The ADC is implemented in 0.18 m CMOS technology and occupies a die area of 0.86 mm 2 . The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, 66.2 dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.

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“…The complete equivalent input noise power of the whole pipeline ADC is (22), and the equivalent input noise power of the S/H circuit must be included. In this case, the gain of the S/H is the unity.…”

Section: Noise In Mdac Stagesmentioning

confidence: 99%

A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

Garcia-Gonzalez¹,

Greitschus²,

Desel³

2009

Analog Integr Circ Sig Process

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This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm CMOS process and it is built by means of a front-end sample-and-hold and a cascade of 10 pipeline stages with 1.5-bits resolution. Performance of 60-dB signal-to-noise-ratio and 68-dB spurious-free-dynamic-range is obtained without calibration at 100-MS/s with a 1-V P-P input signal swing. The occupied silicon area is 0.5-mm 2 ; and the power consumption of 94-mW from a 1.2-V supply.

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A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing

Cited by 10 publications

References 6 publications

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

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