Abstract-A new capacitor and opamp sharing technique that enables a very efficient low power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back in the absence of sample and hold is also presented. Fabricated in a 0.18-µm CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm of active die area and achieves 66.7dB SFDR and 53.2dB SNDR when a 1MHz input signal is digitized at 80MS/s. The SFDR and SNDR are unchanged for 50MHz input signal. The prototype ADC consumes 36mW at 1.8V supply, of which analog portion consumes 24mW. 2
A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 m CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm 2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.Index Terms-Analog-to-digital converter (ADC), capacitor and opamp sharing, data converter, high speed, kickback, low power, memory effect, pipeline.
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