A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from −1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8 × 4.8 mm2 and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit.

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A 14-bit 40-MHz analog front end for CCD application

Wang

Zhu

Liu

2016

J. Semicond.

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A Low Power Digitally Error Corrected 2.5 Bit Per Stage Pipelined a/D Converter Using Current-Mode Signals

Wawryn

Suszyński

Strzeszewski

2011

J CIRCUIT SYST COMP

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This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mode switched-current converter structures. Low power consumption and small chip area are the advantages of the proposed converter.

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A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

Cited by 2 publications

References 19 publications

A 14-bit 40-MHz analog front end for CCD application

A 14-bit 40-MHz analog front end for CCD application

A Low Power Digitally Error Corrected 2.5 Bit Per Stage Pipelined a/D Converter Using Current-Mode Signals

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