A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver

Lee, Kyehyung; Meng, Qingdong; Sugimoto, T.; Hamashita, Koichi; Takasuka, K.; Takeuchi, Shigeyuki; Moon, Un-Ku; Temes, Gábor C.

doi:10.1109/jssc.2008.2012362

Cited by 31 publications

(18 citation statements)

References 14 publications

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“…As part of the digital-to-analog conversion a digital sigma-delta (Σ∆) modulator with Class D output stage is usually used in low-voltage low-power audio applications. This eliminates problems with device matching and reduced power efficiency experienced in case Class AB output stage is used [1,2,3]. The Class D output stage is usually implemented as an H-bridge (schematic in Fig.1 is simplified) and operates in switched mode.…”

Section: System-level Power Optimization For a σ∆ D/amentioning

confidence: 99%

“…The Class D output stage is usually implemented as an H-bridge (schematic in Fig.1 is simplified) and operates in switched mode. Compared to [1,2,3] that use Class AB power stage the Class D allows to perform all signal processing before the output filter in digital domain. Digital design provides the advantage of low-voltage low-power and cost effective implementation and scales down with integrated circuit (IC) technologies of today.…”

Section: System-level Power Optimization For a σ∆ D/amentioning

confidence: 99%

“…Exact comparison can not be performed as the FOM used in the reference works requires finished design. Moreover [1,2,3] use Class-AB power stage and require analog Σ∆ modulator which further complicates comparison at early design stage. Nevertheless trends of the low-voltage low power audio backend designs can be seen in Table III.…”

Section: σ∆ Modulator Design and Comparisonmentioning

confidence: 99%

See 2 more Smart Citations

System-level power optimization for a ΣΔ D/A converter for hearing-aid application

Pracný

Jørgensen

Bruun

2013

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Section: System-level Power Optimization For a σ∆ D/amentioning

confidence: 99%

Section: System-level Power Optimization For a σ∆ D/amentioning

confidence: 99%

Section: σ∆ Modulator Design and Comparisonmentioning

confidence: 99%

See 1 more Smart Citation

System-level power optimization for a ΣΔ D/A converter for hearing-aid application

Pracný

Jørgensen

Bruun

2013

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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“…The idea was introduced as a modification to the first-order interpolating DAC architectures [12][13][14]. Since then, it has been widely adopted in the oversampling ∆Σ DAC (OS∆ΣDAC), for example, [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34]. In digital ∆Σ modulators the input is re-quantized to a shorter word length and the resulting quantization error due to that operation is also spectrally shaped.…”

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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“…Design specifications of such back-end intended for hearing-aid application are covered in Section II. The use of class D PA eliminates problems with device matching and reduced power efficiency experienced in case class AB PA is used [1,2]. The class D PA is usually implemented as an H-bridge (schematic in Fig.1 is simplified) and operates in switched mode with switching frequency f s,PA .…”

Section: Introductionmentioning

confidence: 99%