This paper deals with system-level optimization of a digital-to-analog converter (DAC) for hearing-aid audio Class D output stage. We discuss the ΣΔ modulator system-level design parameters-the order, the oversampling ratio (OSR) and the number of bits in the quantizer. We show that combining a reduction of the OSR with an increase of the order results in considerable power savings while the audio quality is kept. For further savings in the ΣΔ modulator, overdesign and subsequent coarse coefficient quantization are used. A figure of merit (FOM) is introduced to confirm this optimization approach by comparing two ΣΔ modulator designs. The proposed optimization has impact on the whole hearing-aid audio back-end system including less hardware in the interpolation filter and half the switching rate in the digital-pulse-width-modulation (DPWM) block and Class D output stage.
The paper describe a new design for low-voltage CMOS current feedback amplifiers (CFAs). This unconventionally implemented CFA exhibits near gain independent bandwidth. An important feature of the design is that the input resistance looking into the X terminal of the current conveyor is reduced by using an extra opamp. This new architecture results in an amplifier whose bandwidth is potentially constant unlike that of conventional design. Complete analysis and simulation results confirm the design topology. The CFOA operates at supply voltages of ±1.8 V. The circuit exhibits a bandwidth better than 10 MHz. Eldo mentor graphics simulation results using 0.18 μm CMOS technology parameters for the proposed CFOA and its application are discussed.
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