Characterizing Diodes for RF ESD Protection

Chen, Guang; Feng, Haigang; Xie, Hao; Zhan, Rouying; Wu, Qiong; Guan, Xiao; Wang, A.; Takasuka, K.; Tamura, Shigehiko; Wang, Zhihua; Zhang, Chun

doi:10.1109/led.2004.826531

Cited by 25 publications

(12 citation statements)

References 4 publications

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“…2 shows the simulated and measured ESD-induced parasitic capacitances C ESD up to 9 GHz. Unique ground-source-ground (GSG) test patterns were used to ensure measurement accuracy [9]. It is observed that the mixed-mode ESD simulation agrees well with measurement where the slight discrepancy may be removed by further calibration.…”

Section: Rf Esd Protection Designmentioning

confidence: 98%

“…in CMOS for Highly Reliable RF ICs designs [1]- [9]. Such an ESD failure problem is certainly exacerbated by the unique nature of most wireless electronics.…”

Section: Esd-protected Power Amplifier Designmentioning

confidence: 99%

“…In addition, the ESD-induced noise effect can seriously affect the noise performance of RF IC, which is otherwise already a difficult design task for wide band RF ICs. Therefore, careful ESD protection design optimization and ESD-RFIC codesign are essential to ESD-protected RF IC designs at the whole-chip level [1], [3]- [9]. Several RF low-noise amplifier (LNA) designs considering ESD parasitic effects were recently reported, which included the ESD-induced parasitic resistance and capacitance into input impedance matching designs [12]- [14].…”

Section: Esd-protected Power Amplifier Designmentioning

confidence: 99%

“…This is particularly critical to RF ICs that are very sensitive to any parasitic effects. We developed a new mixed-mode ESD simulation-design methodology to achieve ESD protection structure design optimization and a new accurate RF ESD protection design characterization technique to address this design problem [9], [19]. To accurately evaluate ESD-inducted parasitic effects, a group of commonly used ESD protection structures, including diode, silicon-controlled rectifier (SCR), and grounded-gate MOSFET (ggNMOS), were designed for 2-kV HBM ESD protection level and fabricated in a commercial 0.35-μm CMOS technology.…”

Section: Rf Esd Protection Designmentioning

confidence: 99%

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ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

Wang

Guan²,

Fan³

et al. 2011

IEEE Trans. Ind. Electron.

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Electrostatic discharge (ESD) failure is a major reliability problem, and ESD protection is an emerging design challenge for radio-frequency (RF) integrated circuits demanding extremely high reliability for wireless applications in harsh environments. This paper reports the design and optimization of a 5-kV ESD-protected 2.4-GHz power amplifier (PA) circuit in a 0.18-μm RFCMOS technology. A new mixed-mode ESD simulation-design method and an accurate RF ESD characterization technique are used to minimize the inevitable ESD-induced parasitic effects, which can significantly degrade PA circuit performance. A novel ESD-aware PA design technique is utilized to optimize whole-chip ESD + P A performance. Experiments show that conventional ESD protection can seriously affect the PA circuit, while optimized ESD protection may resolve such a problem. The optimized ESD-protected PA circuit achieves good whole-chip performance, including 5-kV ESD protection, a linear output of 13.5 dBm, a gain of 20.2 dB, and a power-added efficiency of ∼18%, all favorable in the same design category.Index Terms-Electrostatic discharge (ESD), integrated circuit (IC), power amplifier (PA), radio frequency (RF).

show abstract

Section: Rf Esd Protection Designmentioning

confidence: 98%

“…in CMOS for Highly Reliable RF ICs designs [1]- [9]. Such an ESD failure problem is certainly exacerbated by the unique nature of most wireless electronics.…”

Section: Esd-protected Power Amplifier Designmentioning

confidence: 99%

Section: Esd-protected Power Amplifier Designmentioning

confidence: 99%

Section: Rf Esd Protection Designmentioning

confidence: 99%

See 2 more Smart Citations

ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

Wang

Guan²,

Fan³

et al. 2011

IEEE Trans. Ind. Electron.

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“…Diode induces low parasitic capacitance and has low cut-in voltage, which are advantages for RF performance and ESD protection, respectively. Silicon-controlled rectifier (SCR) can sustain high ESD current with low parasitic capacitance, too [2]. In addition, I/O ESD clamps with π-match, broadband-architecture, and inductance-resonance techniques have been proposed as ESD protection for RF ICs [3]- [5].…”

Section: Introductionmentioning

confidence: 99%

CMOS Power Amplifier with ESD Protection Design Merged in Matching Network

Shiu

Huang

Ker

2007

2007 14th IEEE International Conference on Electronics, Circuits and Systems

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A power amplifier (PA) with combination of ESD protection circuit and matching network into single block was proposed and implemented in a 0.18-µm CMOS process. By comprising ESD protection function into the matching network, this design omits individual I/O ESD clamps to alleviate loading that degrades RF performances. According to the experimental results, the ESD protection circuit with LC configuration contributes a 3.0-kV human body model (HBM) ESD robustness without significant degradation on RF performances of the PA for 2.4-GHz RF applications.

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Reliability

Azadeh¹

2009

Optical Networks

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Characterizing Diodes for RF ESD Protection

Cited by 25 publications

References 4 publications

ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

CMOS Power Amplifier with ESD Protection Design Merged in Matching Network

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