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Vertical Double Diffused MOSFET (VDMOS) is an established technology for high-current power switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its ability to absorb inductive energy under avalanche conditions. The purpose of this paper is to explore the possibility of improving the ruggedness of VDMOS through TCAD simulations. A p +-strip buried underneath n +-source is proposed to suppress the turn-on of the parasitic bipolar transistor. VDMOS transistors with this design modification is expected to have higher ruggedness while maintained its superior figure-of-merit.

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