Articles you may be interested inCharge trapping properties of the HfO 2 layer with various thicknesses for charge trap flash memory applications Appl. Phys. Lett. 96, 093506 (2010); 10.1063/1.3337103 Reliability of modified tunneling barriers for high performance nonvolatile charge trap flash memory application Appl. Phys. Lett. 96, 043503 (2010); 10.1063/1.3293291 Silicon-oxide-high-κ -oxide-silicon memory using a high-κ Y 2 O 3 nanocrystal film for flash memory application Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxidesemiconductor flash memory Appl. Phys. Lett. 92, 132104 (2008); 10.1063/1.2830000 Three-dimensional self-consistent simulation of the charging time response in silicon nanocrystal flash memoriesThe silicon nitride ͑a-Si x N y :H͒ contact etch stop layer strongly affects data retention performances in single polysilicon nonvolatile memories by acting on the initial charge loss phenomenon. Its improvement has required an analysis of influent plasma enhanced chemical vapor deposition process parameters through a design of experiment approach. The a-Si x N y : H physico-electrical analysis points out that silicon rich compositions especially of its interfacial layer must be avoided to reduce a-Si x N y : H charge amount and as a result to improve the data retention. Indeed, the a-Si x N y : H being near the floating gate, its charges modulation could act as a parasitic memory screening charges stored in the floating gate by capacitive effects.
In this paper, a new characterization methodology of borderless silicon nitride is presented. This material, deposited by a plasmaenhanced chemical vapor deposition process, contains a large charge quantity attributed to K centers. A steady-state capacitancevoltage ͑C-V͒ behavior has been researched, while taking into account charge considerations, electrical field, and time influence. It is achieved by a capacitance vs time at constant voltage experiment after a complete C-V hysteresis used to set up an initial state of charge. The charge evolution occurring during stress time is related to the charge-transformation kinetics. An empirical kinetic model has been extracted from these results, with time constant dependent on field and temperature. A faster positive to negative charge transformation has been shown, attributed to an easier hole trapping. Finally, this new characterization method demonstrates that data retention charge loss is correlated with trapping kinetics in borderless silicon nitride.
In this paper a new characterization methodology of borderless silicon nitride is presented. This material, deposited by Plasma Enhanced Chemical Vapor Deposition process, contains a large charge quantity attributed to K centres. Actually, a steady state has been searched, while taking into account charge considerations, electrical field and time influence during C(V) hysteresis. It is achieved by a capacitance versus time at constant voltage experiment, after a complete C(V) hysteresis used to set up an initial state of charge. The charge evolution occurring during stress time is related to the charge transformation kinetics. An empirical kinetic model has been extracted from these results, with time constant dependent on field and temperature. A faster positive to negative charge transformation has been shown, attributed to an easier holes trapping. Finally, this new characterization method demonstrates that data retention charge loss is correlated to trapping kinetics in borderless silicon nitride.
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