Borderless silicon nitride defect behaviour and their influences on initial data loss in single polysilicon flash memories

New Characterization Methodology of Borderless Silicon Nitride Charge Kinetics Using C-V Hysteresis Loops

“…Second, there is a surprising minority carrier response at high-frequency measurement that is attributed to a permanent inversion layer. 5 Finally, steady-state charge behavior cannot be characterized because of the opening of the hysteresis according to the sweep direction.…”

“…2͒ is positive and equal to 4.5 ϫ 10 −7 , 4.1 ϫ 10 −7 , and 3.9 ϫ 10 −7 C/cm 2 for recipes A, B, and C, respectively. These charges, also extended around the area defined by the gate ͑a-Si x N y :H partially etched during gate etch͒, attract some minority carriers and act as a source and drain reservoir to create the permanent inversion layer, 5 which resulted in the minority carrier response at high-frequency excitation. Charges can be balanced between the two states; for the up-sweep, the charge is largely positive, whereas for the down-sweep, this quantity decreases until reaching a negative sign ͑recipe A: Q up = 1.9 ϫ 10 −6 C/cm 2 , Q down = −1.5 ϫ 10 −8 C/cm 2 ; recipe B: Q up = 1.1 ϫ 10 −6 C/cm 2 , Q down = −4.1 ϫ 10 −8 C/cm 2 ; recipe C: Q up = 1.6 ϫ 10 −6 C/cm 2 , Q down = −3.3 ϫ 10 −7 C/cm 2 ͒.…”

“…However, it is now well known for influencing active device performances: its mechanical stress enables it to improve metal oxide semiconductor ͑MOS͒ transistor performances, 2 but its composition can also be at the origin of reliability issues like charging damage, 3 data retention degradation for single polysilicon flash memory, and high-voltage MOS aging acceleration. 4 In recent studies, it has been reported that a-Si x N y :H composition modifies the dynamic of charge loss in nonvolatile memory, 3 and this wear out has been ascribed to mobile charge in the a-Si x N y :H. 5 In this context, a new methodology is presented in order to determine the trapped charge kinetics in such a film. It is based on capacitance vs time ͑C-t͒ measurements performed on metal insulator semiconductor ͑MIS͒ structures after an initial setup of charge achieved by capacitance vs voltage ͑C-V͒ hysteresis.…”

Contact etch stop a-SixNy:H layer: A key factor for single polysilicon flash memory data retention

“…1 It must be guaranteed over ten years at quite high temperature ͑85°C͒. 5 Thus, the most probable hypothesis is that charges contained in the a-Si x N y : H induced capacitive effects on the FG one. Indeed, the floating gate ͑FG͒ being no longer encapsulated by the control gate, its sensitivity to various process steps increases, increasing charge loss mechanisms.…”

“…However, when considering low cost ͑no added process step͒ single polysilicon ͑SP͒ flash cells, this requirement become even more critical. 3,5 In this context, the aim of this study is to understand how physico-electrical a-Si x N y : H properties impact the SP NVM DR by a design of experiment ͑DOE͒ on PECVD process conditions. Recently, two charge loss phases have been distinguished for such a cell during accelerated 250°C DR bake.…”