We present a high-speed and highly scalable silicon optical modulator based on the free carrier plasma dispersion effect. The fast refractive index modulation of the device is due to electric-field-induced carrier depletion in a Silicon-on-Insulator waveguide containing a reverse biased pn junction. To achieve high-speed performance, a travelling-wave design is used to allow co-propagation of electrical and optical signals along the waveguide. We demonstrate high-frequency modulator optical response with 3 dB bandwidth of ~20 GHz and data transmission up to 30 Gb/s. Such high-speed data transmission capability will enable silicon modulators to be one of the key building blocks for integrated silicon photonic chips for next generation communication networks as well as future high performance computing applications.

Abstract-We present a seamless integration of spin-based memory and logic circuits. The building blocks are magnetologic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and simulate a high-speed, small-area, and low-power spin-based circuit.Index Terms-Network search engines, spintronics.T HE CONTINUED Moore's law scaling in CMOS integrated circuits poses increasing challenges to provide lowenergy consumption, sufficient processor speed, bandwidth of interconnects, and memory storage [1]. Currently, microprocessors rely on the von Neumann architecture consisting of central processing units connected by some communication channel to memory. The bottleneck due to the communication access and memory access is the underlying reason for the widening gap between the fast improving transistor performance and our relatively stagnant programs execution speed. Such bottlenecks are particularly obvious for data-intensive applications, where most of the actions involve accessing or checking data (rather than doing complex computation). Network routers are a classical example where the Internet Protocol address is compared with a list of patterns to find a match. Conventional CMOS implementation of such circuits suffers from scalability issues, making them ineffective for larger search problems that are increasingly important to modern workloads. In this brief, we propose a paradigm change for these applications using spintronics [2]- [5]. We design a 3.2-Mbit spintronic search engine with a < 1 mm 2 total chip area and 23-W power consumption. It consists of 25 000 words of 128 bits. The performance is assessed via circuit simulation. A Magnetologic gate (MLG) is adopted as a basic building block due to its favorable properties of spin amplification, speed, and scalability [2]. Here, we summarize the MLG operation. Detailed explanations are provided in [2] and [6]. Fig. 1 shows a universal and reconfigurable MLG that consists of five ferromagnetic (FM) electrodes on top of a nonmagnetic layer. FM regions are inherently nonvolatile, preserving the direction of magnetization without power supply. This nonvolatility has been extensively used for robust information storage in magnetic hard drives and magnetic random access memory (MRAM) devices [7]. Here, we show how it can also be used for high-performance magnetologic. The magnetization itself reflects that the FM electrode has an unequal number of electrons with two different spin projections (up and down; minority and majority). The MLG design employs a stack of FM layers where the elongated permalloy layer (Py) is the free magnetic layer into which the information is encoded. The MLG operation relies on the generation of nonequilibrium spin accumulation when spin-polarized electrons tunnel from the free layer into the nonmagnetic layer via the MgO tunneling barrier. The magnitude of the spin accumulation in the nonmagnetic layer strongly depends on the relative orientation of the magnetizatio...

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Abstract-This paper presents a new optical interconnect system for intra-chip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 dB and -26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.

Abstract-We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 m and 3 GHz. Simulations show 20-and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC configurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18-m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.

Abstract-We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injectionlocked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18 m digital CMOS technology. It has four divide-by-2 ILOs at the leaves of a 3-section H-tree, generating 5GHz local clocks from the 10GHz input clock with 17% locking range and no phase noise degradation. Measured jitter of generated clocks is lower than that of the input signal. Two local clocks can be differentially deskewed up to 80ps relative to each other. The test chip consumes only 7.3mW excluding test-port buffers.

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.