Abstract-We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 m and 3 GHz. Simulations show 20-and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC configurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18-m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.
Main-stream general-purpose microprocessors require a collection of high-performance interconnects to supply the necessary data movement. The trend of continued increase in core count has prompted designs of packet-switched network as a scalable solution for future-generation chips. However, the cost of scalability can be significant and especially hard to justify for smaller-scale chips. In contrast, a circuit-switched bus using transmission lines and corresponding circuits offers lower latencies and much lower energy costs for smaller-scale chips, making it a better choice than a full-blown network-on-chip (NoC) architecture. However, shared-medium designs are perceived as only a niche solution for small-to medium-scale chips.In this paper, we show that there are many low-cost mechanisms to enhance the effective throughput of a bus architecture. When a handful of highly cost-effective techniques are applied, the performance advantage of even the most idealistically configured NoCs becomes vanishingly small. We find transmission line-based buses to be a more compelling interconnect even for large-scale chipmultiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect.
Cybersecurity's increasing relevance and applicability in the research and development community and job market make it an attractive topic for both students and faculty. Thus, it is necessary for institutions of higher learning to provide courses that prepare students for the broad security-based design space. In addition to teaching students about critical security concepts, hardware-based cybersecurity projects and courses sit at the intersection of many electrical and computer engineering concepts, providing knowledge retention evaluation and assessment opportunities to the instructors and departments. A hardware security course, with optional review-based supplemental work, functions as a culmination of past courses or as an introductory Electrical and Computer Engineering (ECE) course with security-centric applications of foundational concepts.This paper presents the curricular details of an undergraduate hardware security course designed to be self-sufficient and free of advanced prerequisites, thus accessible to a broad student body with a variety of backgrounds. The course covers cryptology, side-channel analysis, hardware Trojan horses, and other hardware-based security exploitations and countermeasures. The course concludes with a multi-week team project where students replicate existing attacks and/or countermeasures, applying their security knowledge and demonstrating skills as ECE professionals. This paper presents the interweaving of ECE topics and evaluation of students' retention of ECE concepts and skills."Hardware Security" has been taught twice in the last year, each time containing around 25 undergraduate students (including electrical, computer, and electromechanical engineers in their third and fourth years). These students were surveyed and evaluated regarding their confidence with and competency of ECE and related concepts at the beginning and end of the course. The data gathered were used to evaluate two metrics: 1) how well students were prepared regarding pre-requisite knowledge; and 2) how the Hardware Security course improved their understanding and confidence of ECE concepts. Student knowledge from previous courses varied, but the post-course data show that students improved their understanding and confidence in various topics. The data also point to possible weaknesses in the students' past courses, which can be used as feedback to improve the respective department curricula. Overall, the course evaluations showed student growth in hardware security and progress in reinforcing ECE fundamental knowledge.The work presented here will help ECE faculty and departments deploy similar curricula to prepare students for a cybersecurity career and provide an evaluation of student conceptual retention and growth within their electrical and computer engineering education.
It is often a challenge to gain insight into undergraduate study habits. Students can list the resources at their disposal and can explain the benefits of well-understood techniques (e.g. study groups, individual meetings/tutoring, time management); however, the same students will often ignore the warning signs of academic trouble and resort to poor habits (e.g., web searches for assignment answers). Additionally, students often believe that the knowledge from class doesn't need to be retained beyond one assignment, quiz, or exam, regardless of if they fail the assignment or evaluation.
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