Enhancing effective throughput for transmission line-based bus

Carpenter, Aaron; Hu, Jianyun; Kocabaş, Övünç; Huang, Michael C.

doi:10.1145/2366231.2337178

Cited by 11 publications

(11 citation statements)

References 47 publications

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“…Transmission Lines (TLs). TLs can provide on-chip broadcast [4,5,10,33,34,41,43]. As a result, they have been used for synchronization.…”

Section: Related Workmentioning

confidence: 99%

“…Abellan et al [4,5] implement locks and barriers using TLs, as they broadcast signals over these TLs. Other designs use TLs for a variety of broadcast networks [10,34,43]. Nanophotonics.…”

Section: Related Workmentioning

confidence: 99%

“…Other Technologies. There are two emerging technologies that can also offer on-chip broadcast capabilities: transmission lines (TLs) [4,5,10,33,34,41,43] and nanophotonics [6,21,23,42,46,47]. While these technologies are more energy-efficient and provide more bandwidth than wireless communication, they are more complicated and less scalable than wireless communication.…”

Section: Introductionmentioning

confidence: 99%

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WiSync

Abadal

Cabellos‐Aparicio

Alarcón

et al. 2016

SIGOPS Oper. Syst. Rev.

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In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support.In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

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“…Transmission Lines (TLs). TLs can provide on-chip broadcast [4,5,10,33,34,41,43]. As a result, they have been used for synchronization.…”

Section: Related Workmentioning

confidence: 99%

“…Abellan et al [4,5] implement locks and barriers using TLs, as they broadcast signals over these TLs. Other designs use TLs for a variety of broadcast networks [10,34,43]. Nanophotonics.…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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WiSync

Abadal

Cabellos‐Aparicio

Alarcón

et al. 2016

SIGOPS Oper. Syst. Rev.

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“…Finally, a recent proposal describes a NoC composed of TL buses, with various optimizations to increase throughput [37]. However, such all-TL approaches increase throughput by using more TLs, complex encoding/decoding to embed more bits in the signal, and/or signaling at extremely high frequencies.…”

Section: B Related Workmentioning

confidence: 99%

Automatic OpenCL work-group size selection for multicore CPUs

Zajić

Prvulovic

2013

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques

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Growth in core count creates an increasing demand for interconnect bandwidth, driving a change from shared buses to packet-switched on-chip interconnects. However, this increases the latency between cores separated by many links and switches. In this paper, we show that a low-latency unswitched interconnect built with transmission lines can be synergistically used with a high-throughput switched interconnect. First, we design a broadcast ring as a chain of unidirectional transmission line structures with very low latency but limited throughput. Then, we create a new adaptive packet steering policy that judiciously uses the limited throughput of this ring by balancing expected latency benefit and ring utilization. Although the ring uses 1.3% of the on-chip metal area, our experimental results show that, in combination with our steering, it provides an execution time reduction of 12.4% over a mesh-only baseline.

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“…Packet switching on high radix network topologies exacerbates this problem due to the energy and latency overhead contributed by switches and routers. Alternative network fabrics utilizing low latency, low energy buses have shown promise in circumventing this problem [1]. Transmission lines (TL) are possibly the most suitable building blocks for bus-based topologies since they provide fast, low energy long distance communication using present generation CMOS devices and techniques.…”

mentioning

confidence: 99%

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm

Das

Manetas

Stevens

et al. 2013

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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Abstract-Implementation of low energy, low latency transmission line interconnects on a network-on-chip presents the circuit designer with a variety of structural design choices. This work presents a study of the comparative effects of changing the wire geometries on the latency, energy dissipated, area, and noise properties of the transmission lines. These results will aid the engineer in the design and performance analysis of the global interconnect and foster a quantitative understanding of the wave signaling properties in the RLC regime.Energy dissipation in wires has become a primary bottleneck for the continued scaling of future interconnect networks. Packet switching on high radix network topologies exacerbates this problem due to the energy and latency overhead contributed by switches and routers. Alternative network fabrics utilizing low latency, low energy buses have shown promise in circumventing this problem [1]. Transmission lines (TL) are possibly the most suitable building blocks for bus-based topologies since they provide fast, low energy long distance communication using present generation CMOS devices and techniques. Reliable on-chip implementation of TL interconnects requires substantial analysis and careful design, often with the help of complex full-wave field solvers. Characterization of transmission lines is a well studied subject [2] [3] [4]; however, a direct relation between the physical and geometric properties of a TL link design and its effectiveness as a communication medium is not available. This work aims at providing an insight into the various trade-offs between the performance of global RLC wires and their geometric properties. The case study presented here is intended to serve as a guide for link designers to better understand the available design choices supplemented with numerical data.RC representations of long wires are rendered inaccurate due to high frequency inductance effects. Electromagnetic field solvers are required for analyzing the behavior of transmission lines in order to include second order effects such as substrate coupling. Since accuracy trumps solution time in this study, a 3D full wave solver is employed for the analyses [5]. Scattering (S) parameters are extracted from the TL geometries for a frequency range of 100 MHz to 100 GHz and written to a Touchstone file for over 50 different transmission line structures. Transient analyses are performed on these extracted values in Synopsys HSPICE using CMOS drivers and loads. The back end of the line (BEOL) arrangement from the Global Foundries 65nm LPE process, complete with a hierarchical dielectric structure, low resistivity substrate and dense lower metal layers, is used as the guide to set up the simulation environment. Tab.

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Enhancing effective throughput for transmission line-based bus

Cited by 11 publications

References 47 publications

WiSync

WiSync

Automatic OpenCL work-group size selection for multicore CPUs

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm

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