Injection-Locked Clocking: A New GHz Clock Distribution Scheme

Abstract

Abstract-We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injectionlocked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18 m digital CMOS technology. It has four divide-by-2 ILOs at the leaves of a 3-section H-tree, generating 5GHz local clocks from the 10GHz input clock with 17% locking range and no phase noise degradation. Measured jitter of generated clocks is lower than that of the input signal. Two local clocks can be differentially deskewed up to 80ps relative to each other. The test chip consumes only 7.3mW excluding test-port buffers.

Active deskew in injection-locked clocking

“…The key for such an active deskew scheme is the phase tuning capability of ILOs, which has been demonstrated in our previous work [1], [14], [15]. As shown in Fig.…”

“…Therefore, we propose a new active deskew scheme that utilizes the phase tuning capability of ILOs to compensate the skew [1], [15]. This deskew scheme does not require the additional deskew delay lines and hence does not suffer in clock latency and jitter while consuming minimal extra power.…”

“…Injection-locked clocking (ILC) has been proposed for multi-GHz clock distribution [1], which uses injection-locked oscillators (ILO) as local clock generators. Compared to conventional clocking based on buffered trees and grids, it can achieve lower jitter while consuming less power [2].…”

A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking

“…Injection-locked clocking (ILC) [4] has been proposed for multi-GHz clock distribution to address these problems. With the high sensitive injection-locked oscillator (ILO) as the local clock regenerator, ILC can use a much smaller voltage on the global clock distribution network.…”

“…In the previous ILC test chip reported [4], divide-by-2 ILOs (Fig. 1a) were used simply because the design was readily available.…”