The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

We investigated the effects of the interface state density (DIT) at the interfaces between SiO2 and the Si-, C-, and a-faces of 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. The interface state density over a very shallow range from the conduction band edge (0.00 eV < EC − ET) was evaluated on the basis of the subthreshold slope deterioration at low temperatures (11 K < T). The interface state density continued to increase toward EC, and DIT at EC was significantly higher than the value at the conventionally evaluated energies (EC − ET = 0.1–0.3 eV). The peak field-effect mobility at 300 K was clearly inversely proportional to DIT at 0.00 eV, regardless of the crystal faces and the oxidation/annealing processes.

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

The reliability of thermal oxides grown on an n-type 4H-SiC(0001) was investigated using an area-scaling method, and the influence of dislocation defects on the time-dependent dielectric breakdown characteristics of thermal oxides was examined. A thermal oxide was grown by dry oxidation at 1200 C followed by nitrogen post-oxidation annealing. Using the area-scaling method, the time-to-breakdown (t BD ) distribution curves of metal-oxide-semiconductor (MOS) capacitors with different gate area sizes were converged to a single one. It was clearly shown that origins of dielectric breakdown are edge breakdown and dislocation-related breakdown for steep and gradual slopes of the area-scaling normalized t BD distribution curve, respectively. In addition, a yield analysis of MOS capacitors quantitatively indicated that both threading screw dislocation and basal plane dislocation are predominant killer defects for the dielectric breakdown of thermal oxides on the 4H-SiC(0001) face.

Articles you may be interested inInfluence of the surface morphology on the channel mobility of lateral implanted 4H-SiC (0001) metal-oxidesemiconductor field-effect transistors J. Appl. Phys. 112, 084501 (2012); 10.1063/1.4759354 Effect of the oxidation process on the electrical characteristics of 4 H -Si C p -channel metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 89, 023502 (2006); 10.1063/1.2221400 Correlation between channel mobility and shallow interface traps in SiC metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 92, 6230 (2002); 10.1063/1.1513210Relationship between channel mobility and interface state density in SiC metal-oxide-semiconductor field-effect transistor A cause for highly improved channel mobility of 4H-SiC metal-oxide-semiconductor field-effect transistors on the (1120) face Appl.

We have evaluated interface state density (DIT) for EC−ET > 0.00 eV from the subthreshold slope deterioration of MOSFETs at low temperatures. We have compared two n-channel MOSFETs on the C- and a-faces with the gate oxide formed by pyrogenic oxidation followed by annealing in H2. The peak field-effect mobility (µFE,peak) for the C-face MOSFET was 57 cm2V-1s-1 at 300 K, which is lower than the half of 135 cm2V-1s-1 for the a-face MOSFET. We have shown that DIT very close to EC can well explain why µFE for C-face MOSFETs is lower than that for a-face MOSFETs. The value of DIT at 0.00 eV corresponding to the subthreshold slope at 11 K was 1.6×1014 cm-2eV-1 for the C-face MOSFET, which is more than the double of 6.4×1013 cm-2eV-1 for the a-face MOSFET.

The effect of ammonia (NH3) post-oxidation annealing (POA) technique on the reliability of thermal oxides grown on a n-type 4H-SiC (0001) face by dry oxidation has been investigated. Comparing other POA techniques using hydrogen and nitrous oxide gases, it was indicated that the NH3 POA after dry oxidation remarkably improves the insulating properties of thermal oxides. The mode value of field-to-breakdown for thermal oxides prepared by NH3 POA was 12.1 MV/cm. The charge-to-breakdown (QBD) in the NH3 POA sample was the highest in all samples, and the QBD value at 63% cumulative failure rate was 19.1 C/cm2. In addition, the NH3 POA maintained excellent electron trapping characteristics of thermal oxides against the electron injection.

Threshold voltage (VTH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on VTH instability is also discussed. Nitridation treatments such as N2O and NH3 post-oxidation annealing (POA) are effective in stabilization of VTH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious VTH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H2 POA.