Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers

Abstract

The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

Phase and microstructure analysis by electron diffraction in semiconductor failure analysis

“…[4][5]. It has been reported that charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations.…”

“…It has been reported that charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations. [4] Therefore, the dislocations observed in the bad unit may be the root cause for the early breakdown of the power MOS.…”

“…To clearly indentify the interface between Si, Si plasmon EFTEM imaging at energy win centered at 17.5Ev were taken as shown in Fig.4 orm WO 4 2 (d)…”

Impact of Morphological Features on the Dielectric Breakdown at SiO[sub 2]∕3C-SiC Interfaces

“…However, the reliability and premature BD generation mechanisms in thermal oxides grown on 3C-SiC has not been addressed. In addition to the intrinsic properties of the dielectric, the BD event is controlled by defects on the semiconductor surface, the conduction band offset at the semiconductor/SiO 2 interface, and oxidation and post oxidation conditions [3,5]. The nature of the defects, the conduction band offset and the optimal oxidation and post oxidation conditions [6] are different for 3C-SiC compared to the better studied 4H polytype.…”

Correlation between surface morphology and breakdown characteristics of thermally grown SiO<inf>2</inf> dielectrics in 4H-SiC MOS devices

“…However, one of the key obstacles in SiC-based MOS devices is poor gate oxide reliability. It has been pointed out that the dielectric breakdown of SiO 2 on 4H-SiC(0001) substrates mainly occurs at basal plane dislocation in the epilayer during constant voltage time-dependent dielectric breakdown (TDDB) measurement [1]. Meanwhile, our conductive atomic force microscopy (C-AFM) study on a thermally grown SiO 2 /4H-SiC(0001) structure has clearly demonstrated that dielectric breakdown is preferentially induced at the step bunching [2].…”