Articles you may be interested inA methodology to identify and quantify mobility-reducing defects in 4H-silicon carbide power metal-oxidesemiconductor field-effect transistors Influence of the surface morphology on the channel mobility of lateral implanted 4H-SiC (0001) metal-oxidesemiconductor field-effect transistors J. Appl. Phys. 112, 084501 (2012); 10.1063/1.4759354 Effect of nitric oxide annealing on the interface trap density near the conduction bandedge of 4H-SiC at the oxide /(1120) 4H-SiC interface Effects of anneals in ammonia on the interface trap density near the band edges in 4H-silicon carbide metaloxide-semiconductor capacitors

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The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

Temperature dependence of threshold voltage in n-channel SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) was studied. Linear relation was observed between the threshold voltage shift when the temperature varies from −150 to 150 °C and the number of the interface states present within the energy range of 0.2–0.4 eV from the conduction band edge energy Ec. This relationship revealed that the interface state profile near Ec in n-channel SiC MOSFETs can be represented by that in n-type SiC MOS capacitors. The relationship between the channel mobility and the interface state profile also suggested that the interface states within the energy range of 0.2–0.4 eV from Ec have little influence on the channel mobility.

The origin of expanded single Shockley-type stacking faults in forward-current degradation of 4H-SiC p-i-n diodes was investigated by the stresscurrent test. At a stress-current density lower than 25 A cm %2 , triangular stacking faults were formed from basal-plane dislocations in the epitaxial layer. At a stress-current density higher than 350 A cm %2, both triangular and long-zone-shaped stacking faults were formed from basal-plane dislocations that converted into threading edge dislocations near the interface between the epitaxial layer and the substrate. In addition, the conversion depth of basal-plane dislocations that expanded into the stacking fault was inside the substrate deeper than the interface. These results indicate that the conversion depth of basal-plane dislocations strongly affects the threshold stress-current density at which the expansion of stacking faults occurs.

We investigated the effects of the interface state density (DIT) at the interfaces between SiO2 and the Si-, C-, and a-faces of 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. The interface state density over a very shallow range from the conduction band edge (0.00 eV < EC − ET) was evaluated on the basis of the subthreshold slope deterioration at low temperatures (11 K < T). The interface state density continued to increase toward EC, and DIT at EC was significantly higher than the value at the conventionally evaluated energies (EC − ET = 0.1–0.3 eV). The peak field-effect mobility at 300 K was clearly inversely proportional to DIT at 0.00 eV, regardless of the crystal faces and the oxidation/annealing processes.

The formation of extended defects in the 4H–SiC epilayer induced by the implantation/annealing process was investigated using synchrotron reflection x-ray topography, KOH etching analysis, and transmission electron microscopy. High temperature annealing was performed for the 4H–SiC epilayer with or without the implantation of nitrogen or aluminum ions. Other than the formation of platelet extrinsic Frank-type faults in the implanted region as reported previously, we find the formation modes of extended defects in following three categories: (i) dislocation formation near the epilayer/substrate interface, (ii) dislocation formation near the implanted region, and (iii) the formation of Shockley-type defects near the surface. The defect morphology and process dependence of each type are also discussed.

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500 C. The optimum doping depth of the BC region has been investigated. For the nitrogen concentration of 1 10 17 cm 3 , the optimum depth was found to be 0.2 m. Under this condition, the channel mobility of 140 cm 2 /Vs was achieved with the threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide.Index Terms-4H-SiC, buried channel (BC), channel mobility, MOSFET.