High channel mobility in normally-off 4H-SiC buried channel MOSFETs

Abstract

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500 C. The optimum doping depth of the BC region has been investigated. For the nitrogen concentration of 1 10 17 cm 3 , the optimum depth was found to be 0.2 m. Under this condition, the channel mobility of 140 cm 2 /Vs was achieved with the threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide.Index Terms-4H-SiC, buried channel (BC), channel mobility, MOSFET.

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

“…At room temperature, the field-effect mobility l FE reaches a peak value as high as 95 cm 2 /V s at the oxide field around 1 MV/cm, representing a significant improvement in the channel mobility compared to the results in [3,4], which were subjected to similar high-temperature ohmic contact rapid thermal annealing. It is worth pointing out that this result is more meaningful for fabrication of MOSFETs than those higher mobilities of 140-150 cm 2 /V s in [5][6][7], because those results were only obtained without high-temperature ohmic contact annealing. The field-effect mobility l FE at 200°C as shown in Fig.…”

“…The fact that gate oxide needs to be formed on the source region which usually has a substantial surface roughness due to the heavy dose nitrogen implantation and high-temperature annealing also gives rise to the concerns of gate oxide reliability. Recently, various approaches have been employed to improve the quality of the MOS interface [2][3][4][5][6][7]. Peak inversion channel mobilities of 50-70 cm 2 /V s [3,4] have been obtained by the nitridation of SiO 2 /SiC interface through nitric oxide (NO) growth or NO annealing.…”

“…However, there are problems associated with this special process: Rapid thermal annealing for ohmic contacts has to be avoided to attain the above results, or the channel mobility would be degraded by a factor of about two [6]; substantial mobile ions may have been introduced into gate oxide under the contaminated alumina environment [5]. In addition, some researchers utilized a buried channel structure formed by ion implantation to improve the channel mobility in 4H-SiC MOSFETs with up to 140 cm 2 /V s reported [7]. Similar to [5], however, this high mobility was only obtained without high-temperature ohmic contact annealing, which, however, is an inevitable processing step needed for MOS-FET fabrication.…”

“…Unlike all published works [3][4][5][6][7][8], the structure of lateral trench-gate MOSFET contains the novel features aiming at improving channel mobility and gate oxide reliability: no N + source implantation and hence no high-temperature (P1550°C) surface-degrading activation annealing are needed throughout the fabrication; no epitaxial regrowth is required; and no MOS channel implantation is performed. It will be reported that truly normally-off MOSFETs under accumulation mode can achieve the high channel mobility of 95 cm 2 /V s and 255 cm 2 /V s at room temperature and 200°C, respectively.…”

A 4.3−mΩcm2, 1100‐V normally‐off IEMOSFET on SiC

“…In SiC-MOSFET, the mobility of inversion channel drops because of numerous SiO 2 /SiC interface states. In the case of a buried channel, this effect is inhibited, and the channel mobility is improved, by extending the channel inside the substrate [6,7].…”