Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

N-channel field-effect mobility inversely proportional to the interface state density at the conduction band edges of SiO2/4H-SiC interfaces

“…Figure 2 shows the µ FE of these MOSFETs at 300 K. As described in the literature, 5,[8][9][10] the characteristics on the a-face were considerably better than those on the other faces. The characteristics on the Si-face were the most inferior, and almost no current flowed at 11 K .…”

“…However, the low channel currents at the SiO 2 /4H-SiC interfaces remain an important issue, despite extensive studies for more than a decade. [1][2][3][4][5][6][7][8][9][10] Although the interface states have been assumed to be a main cause of the low channel current, 2,3,6,7,10,16 a clear correlation between the interface state density (D IT ) and the channel performance has not been determined. 11 We recently showed that the peak n-channel field-effect mobility (µ FE,peak ) at room temperature is roughly inversely proportional to D IT for samples on the (0001), (000-1), and (11)(12)(13)(14)(15)(16)(17)(18)(19)(20) faces (the Si-, C-, and a-faces, respectively) after dry/nitridation and pyrogenic/hydrotreatment processes, 12 where D IT was evaluated by the C−ψ S method 13 at 0.2 eV below the conduction band edge (E C −E T = 0.2 eV) using MOS capacitors.…”

“…9,[14][15][16] Because the Fermi energy (E F ) at the interface that corresponds to the subthreshold region approaches E C with decreasing temperature, D IT at energies nearer E C can be evaluated from the subthreshold slope at lower temperatures. In this study, we evaluate D IT over the very shallow range of 0.00 eV <E C −E T based on the deterioration of the subthreshold slope by decreasing the temperature to 11 K, and show the correlation between D IT near E C and µ FE,peak at 300 K.…”

Photoelectron Nano-spectroscopy of Reactive Ion Etching-Induced Damages to the Trench Sidewalls and Bottoms of 4H-SiC Trench-MOSFETs

“…[2] Furthermore, the non-polar 1100 plane (mplane) of 4H-SiC can offer the highest channel mobility among various SiC crystal planes [3] and can be used as a channel plane for the trench sidewall in trench-gate MOSFETs. [4] However, we observe that only a few reports have been published regarding the effects of MOS channel planes, considerably affecting the MOS channel properties and the overall MOSFET performance. [5] Till date, sev-eral studies have been conducted to investigate the influences of etching conditions [6][7][8], etched contamination, and damages [9][10][11] on RIE etching performance.…”

“…It has additionally been reported that the thickness of polymer-like layers is drastically decreased as the ratio of O 2 in the etching gases of CF 4 and C 2 F 6 increases. These polymerlike layers that are observed during the SiC trench formation are assumed to be formed during the re-deposition of CF 4 or CF x species from the etched bottom plane. Further, we observed that the etching was enhanced using O 2 admission, suggesting the importance of O 2 to eliminate or reduce other residues such as SF x , SiF x , and CF x compounds from the etched bottom surface.…”