Evaluation of 4H-SiC Thermal Oxide Reliability Using Area-Scaling Method

Abstract

The reliability of thermal oxides grown on an n-type 4H-SiC(0001) was investigated using an area-scaling method, and the influence of dislocation defects on the time-dependent dielectric breakdown characteristics of thermal oxides was examined. A thermal oxide was grown by dry oxidation at 1200 C followed by nitrogen post-oxidation annealing. Using the area-scaling method, the time-to-breakdown (t BD ) distribution curves of metal-oxide-semiconductor (MOS) capacitors with different gate area sizes were converged to a single one. It was clearly shown that origins of dielectric breakdown are edge breakdown and dislocation-related breakdown for steep and gradual slopes of the area-scaling normalized t BD distribution curve, respectively. In addition, a yield analysis of MOS capacitors quantitatively indicated that both threading screw dislocation and basal plane dislocation are predominant killer defects for the dielectric breakdown of thermal oxides on the 4H-SiC(0001) face.

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

“…In particular, C-AFM allowed determining the morphological shape of the surface (Fig. 4a) -a triangle with the vertex in the [11][12][13][14][15][16][17][18][19][20] direction -about 25 nm deeper than the surface of the JFET region where it is located. Even in the triangular region (highlighted with a dashed line), the surface conductivity is rather homogeneous (Fig.…”

“…3) allowed to identify a threading dislocation (TD) running along the epitaxial layer. The TEM dual beam investigation -along the directions[11][12][13][14][15][16][17][18][19][20] and [0002], shown in Figs. 3a and 3b, demonstrated the presence of a mixed dislocation.…”

Defect engineering in SiC technology for high-voltage power devices

“…Meanwhile, there has been debate on the correlation between dielectric breakdown of the gate oxides and structural defects in SiC substrates, such as dislocations and surface morphology. [185][186][187][188][320][321][322] Figures 36(a) and 36(b) show cross-sectional TEM images around steps on the asgrown SiC surface and SiO 2 /SiC interface formed on the surface by dry oxidation at 1100 °C for 12 h. 323) As shown in the magnified images, single steps were observed at the SiO 2 /SiC interface, indicating elimination of step bunching with the progress of thermal oxidation. Moreover, to confirm the impact of the initial surface roughness on the oxide surface and interface structure, significant step bunching was intentionally induced by high-temperature annealing at 1700 °C.…”

Nanoscale Insights on the Origin of the Power MOSFETs Breakdown after Extremely Long High Temperature Reverse Bias Stress

“…3a and 3b allowed to establish the mixed nature of the dislocation. In particular, the dislocation shows up with the [11][12][13][14][15][16][17][18][19][20] spot (edge) and with the [0002] spot (screw). In fact, it was unclear whether threading dislocations (screw and edge) behave as killer defects in 4H-SiC MOSFETs.…”

“…On the other hand, surface defects, like down-falls, carrots and step-bunching, produce the appearance of the extrinsic breakdown population (low charge-to-breakdown). However, the role of threading dislocations (threading screw dislocations (TSDs) and threading edge dislocations (TEDs)) as killer defects for 4H-SiC MOSFETs is still unclear [13,14].…”