Effects of interface state density on 4H-SiC n-channel field-effect mobility

Abstract

Articles you may be interested inInfluence of the surface morphology on the channel mobility of lateral implanted 4H-SiC (0001) metal-oxidesemiconductor field-effect transistors J. Appl. Phys. 112, 084501 (2012); 10.1063/1.4759354 Effect of the oxidation process on the electrical characteristics of 4 H -Si C p -channel metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 89, 023502 (2006); 10.1063/1.2221400 Correlation between channel mobility and shallow interface traps in SiC metal-oxide-semiconductor field-effect transistors J. Appl. Phys. 92, 6230 (2002); 10.1063/1.1513210Relationship between channel mobility and interface state density in SiC metal-oxide-semiconductor field-effect transistor A cause for highly improved channel mobility of 4H-SiC metal-oxide-semiconductor field-effect transistors on the (1120) face Appl.

High channel mobility of 3C-SiC n-MOSFETs with gate stacks formed at low temperature—the importance of Coulomb scattering suppression

“…For correct D it evaluation from MOS capacitors, more appropriate measurement methods, such as the conductance method or the capacitance-surface potential (C-ψ S ) method, should be used. 3,25) In any case, the results suggest that electron trapping and Coulomb scattering by the IT in the SiO 2 /Al 2 O 3 gate insulator may not be significant compared with the SiO 2 /plasma oxi.-IL. An NIT is enumerated as another candidate for the electron trapping Table I.…”

“…It is a common phenomenon for SiC gate stacks, and the reason is the underestimation (better than the actual value) of the high-low method. [24][25][26] It means many interface states can respond to even high-frequency measurement, which is different from the ideal high-low method. For correct D it evaluation from MOS capacitors, more appropriate measurement methods, such as the conductance method or the capacitance-surface potential (C-ψ S ) method, should be used.…”

Reduction of interface states by hydrogen treatment at the aluminum oxide/4H-SiC Si-face interface

“…Optimization of processes such as the plasma pretreatment time (discussed in the next paragraph) enabled a lower D IT (C−ψ S , 0.2eV) of 1.7×10 12 cm 2 eV 1 to be achieved compared with 36×10 12 cm 2 eV 1 for conventional samples of the dry oxide with NO annealing (Dry/NO). 22,23 The difference in the quasi-static and 100 kHz capacitances of approximately 3 pF at the accumulation region is relatively large compared with that for the conventional Dry/NO samples. Although accurate evaluation of the trap density distribution is difficult for the accumulation region, the large capacitance difference indicates that slow traps that cannot respond at 100 kHz exist near the conduction band edge.…”

“…A peak mobility of 57 cm 2 V 1 s 1 is reasonable because the relationship between µ FE,peak (= 57 cm 2 V 1 s 1 ) and D IT (0.2 eV) (= 1.7×10 12 cm 2 eV 1 ) is on the correlation line for the Si-and C-face samples. 23 Although the processes were designed to exclude SiO 2 at the interface, 57 cm 2 V 1 s 1 is not very high, which indicates the existence of interface states other than SiO 2 -related traps.…”

3D structures for silicon carbide transistors utilising Al2O3 as a gate dielectric

“…For the multi -m scale MOSFETs being researched at the present time, one of the main technological concerns in 4H-SiC technology is that of electrically active defects at the SiO 2 /SiC interface, leading to a high density of interface states ( ) near the conduction band edge, resulting in low effective inversion channel mobility [8,9]. This appears to reduce capability of 4H-SiC MOSFETs, which means that the performance is below that predicted theoretically.…”