Threshold Voltage Instability of SiC-MOSFETs on Various Crystal Faces

Abstract

Threshold voltage (VTH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on VTH instability is also discussed. Nitridation treatments such as N2O and NH3 post-oxidation annealing (POA) are effective in stabilization of VTH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious VTH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H2 POA.

Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method

“…Actually, by high-speed drain current vs gate-source voltage (I d -V g ) measurement, a large V th shift induced by the positive bias stress has been observed. 8,9) Although many studies on positive gate bias stress have been reported, [7][8][9][10][11][12][13][14][15][16][17][18] there are only a few studies on negative gate bias stress. [19][20][21][22][23] In addition to detrapping phenomena, negative bias temperature stress instability is possibly underestimated by the conventional I d -V g method because the holes trapped by negative stress are recombined with channel electrons owing to the positive V g bias during I d -V g measurement.…”

Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions

“…[13][14][15][16][17][18] Furthermore, SiC MOSFETs show V th shifts under positive and negative gate bias stresses owing to the large number of interface and near-interface defects. [19][20][21][22][23][24][25][26][27][28][29] A positive V th shift due to a positive gate bias stress reduces the drain current (I d ) during the on-state, and a negative V th shift due to a negative gate bias stress causes unintentional turning on. A V th shift occurs because of the injection of channel charges into the gate oxide and=or the generation of interface states owing to gate stress.…”

Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

“…The threshold-voltage (V th ) instability under gate stress, which can be characterized by a bias temperature instability (BTI) measurement, is one of the most important issues in SiC MOS devices. [3][4][5][6][7][8][9] V th shift occurs because of the injection of channel charges into the gate oxide and=or the generation of interface states due to gate stress. [10][11][12] The injected charges in the bulk SiO 2 and the near-interface region are transiently released after the gate stress is removed.…”

“…In a general BTI measurement, V th is separately measured after gate-stress removal. 5,8) Therefore, V th is recovered during the gate-voltage sweep for V th measurement because the trapped charges are immediately released. Thus, V th relaxation results in underestimation in the V th shifts due to the gate stress.…”