Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions

Sometani, Mitsuru; Okamoto, Mitsuo; Hatakeyama, Tatsuko; Iwahashi, Yohei; Hayashi, Mariko; Okamoto, Daisuke; Yano, Hiroshi; Harada, Shinsuke; Yonezawa, Yoshiyuki; Okumura, Hajime

doi:10.7567/jjap.57.04fa07

Cited by 12 publications

(9 citation statements)

References 50 publications

(72 reference statements)

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“…To overcome this problem, by referring to the BTI measurements without V T relaxation of state-of-theart Si MOS devices, 330,331) the non-relaxation method was applied to various SiC MOSFETs and an accurate evaluation of the fast V T shift under the various stressing conditions has recently been made. 243,332,333) This advanced non-relaxation method detected extremely large V T shifts in…”

Section: Reliability Of Sic Mos Devicesmentioning

confidence: 99%

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Defect engineering in SiC technology for high-voltage power devices

Kimoto

Watanabe

2020

Appl. Phys. Express

187

100

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Major features of silicon carbide (SiC) power devices include high blocking voltage, low on-state loss, and fast switching, compared with those of the Si counterparts. Through recent progress in the material and device technologies of SiC, production of 600–3300 V class SiC unipolar devices such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes has started, and the adoption of SiC devices has been demonstrated to greatly reduce power loss in real systems. However, the interface defects and bulk defects in SiC power MOSFETs severely limit the device performance and reliability. In this review, the advantages and present status of SiC devices are introduced and then defect engineering in SiC power devices is presented. In particular, two critical issues, namely defects near the oxide/SiC interface and the expansion of single Shockley-type stacking faults, are discussed. The current physical understanding as well as attempts to reduce these defects and to minimize defect-associated problems are reviewed.

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Section: Reliability Of Sic Mos Devicesmentioning

confidence: 99%

“…the short-stress-time regions under positive and negative stress conditions. 333) 4. Understanding and engineering of bipolar degradation in SiC devices…”

Section: Reliability Of Sic Mos Devicesmentioning

confidence: 99%

Defect engineering in SiC technology for high-voltage power devices

Kimoto

Watanabe

2020

Appl. Phys. Express

187

100

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“…Particularly, MOSFETs require threshold voltage (V th ) stability to ensure safety operation. [19][20][21] Since V th shift is mainly caused by charges trapped in the oxide, oxide traps and their precursors must be reduced as much as possible. The possible causes of these traps are C-related defects 3) and oxygen vacancies 22) within the SiO 2 near SiO 2 /SiC interface.…”

mentioning

confidence: 99%

High-temperature CO₂ treatment for improving electrical characteristics of 4H-SiC(0001) metal-oxide-semiconductor devices

Hosoi

Ohsako

Shimura

et al. 2021

Appl. Phys. Express

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High-temperature CO2 treatments for 4H-SiC(0001) surfaces and SiO2/SiC structures were investigated. A stoichiometric SiO2 insulating layer was found to be grown on SiC by thermal oxidation in atmospheric CO2 ambient with an activation energy of 7.5 eV. Post-oxidation annealing (POA) in CO2 at a temperature of 1200 °C or more was effective in reducing interface fixed charges, oxide traps, and defect precursors, which are intrinsically involved in SiO2/SiC system grown with O2 oxidant. Furthermore, modification of the SiO2/SiC interface promoted by oxidizing SiC with CO2 at 1400 °C or more reduced the amount of interface states, thus the SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) treated with CO2 at 1400 °C exhibited improved channel mobility with a stable threshold voltage.

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“…The breakdown voltage is a linear function of the residual charge after ion orbital recombination [99,100] PLL/HIRFL…”

Section: Object/methods Content Conclusion Referencementioning

confidence: 99%

“…However, the physical mechanisms of the capacitor SEGR response have not been well studied. The capacitor SEGR response was studied by Sexton et al based on the concept of the plasma pipe [98][99][100][101][102][103]. A model to describe the transient electric field induced by the ion strike in oxide was proposed by Luo Y.H.…”

Section: Influence Of High-energy Particles On Semiconductor Devicesmentioning

confidence: 99%

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions

Cited by 12 publications

References 50 publications

Defect engineering in SiC technology for high-voltage power devices

Defect engineering in SiC technology for high-voltage power devices

High-temperature CO₂ treatment for improving electrical characteristics of 4H-SiC(0001) metal-oxide-semiconductor devices

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

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Accurate evaluation of fast threshold voltage shift for SiC MOS devices under various gate bias stress conditions

Cited by 12 publications

References 50 publications

Defect engineering in SiC technology for high-voltage power devices

Defect engineering in SiC technology for high-voltage power devices

High-temperature CO2 treatment for improving electrical characteristics of 4H-SiC(0001) metal-oxide-semiconductor devices

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

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High-temperature CO₂ treatment for improving electrical characteristics of 4H-SiC(0001) metal-oxide-semiconductor devices