Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

Sometani, Mitsuru; Okamoto, Daisuke; Harada, Shinsuke; Ishimori, Hitoshi; Takasu, Sachiko; Hatakeyama, Tatsuko; Takei, Masahiro; Yonezawa, Yoshiyuki; Fukuda, Kenji; Okumura, Hajime

doi:10.7567/jjap.55.04er11

Cited by 28 publications

(30 citation statements)

References 27 publications

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“…To overcome this problem, by referring to the BTI measurements without V T relaxation of state-of-theart Si MOS devices, 330,331) the non-relaxation method was applied to various SiC MOSFETs and an accurate evaluation of the fast V T shift under the various stressing conditions has recently been made. 243,332,333) This advanced non-relaxation method detected extremely large V T shifts in…”

Section: Reliability Of Sic Mos Devicesmentioning

confidence: 99%

Defect engineering in SiC technology for high-voltage power devices

Kimoto

Watanabe

2020

Appl. Phys. Express

187

100

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Major features of silicon carbide (SiC) power devices include high blocking voltage, low on-state loss, and fast switching, compared with those of the Si counterparts. Through recent progress in the material and device technologies of SiC, production of 600–3300 V class SiC unipolar devices such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes has started, and the adoption of SiC devices has been demonstrated to greatly reduce power loss in real systems. However, the interface defects and bulk defects in SiC power MOSFETs severely limit the device performance and reliability. In this review, the advantages and present status of SiC devices are introduced and then defect engineering in SiC power devices is presented. In particular, two critical issues, namely defects near the oxide/SiC interface and the expansion of single Shockley-type stacking faults, are discussed. The current physical understanding as well as attempts to reduce these defects and to minimize defect-associated problems are reviewed.

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Section: Reliability Of Sic Mos Devicesmentioning

confidence: 99%

Defect engineering in SiC technology for high-voltage power devices

Kimoto

Watanabe

2020

Appl. Phys. Express

187

100

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“…[3][4][5] The traps located near the interface are considered to be responsible for the fast relaxation of the threshold voltage (V th ) shift in SiC MOSFETs. 6) Therefore, investigation of NITs is very important. The NITs on SiC have been evaluated; [7][8][9][10][11] however, the spatial distribution of NITs is not considered in conventional analysis methods, and the nature of NITs remains under debate.…”

mentioning

confidence: 99%

“…32) In addition, the significant NIT density decrease with increasing nitridation time is consistent with the results reported by Sometani et al, in which fast V th shift values were reduced by nitridation, compared with those of dry samples. 6) In conclusion, the NITs in SiO 2 =4H-SiC MOS structures were investigated using a distributed circuit model. It was found that this model can be applied to SiC MOS capacitors, but we must assume an exponential NIT distribution to explain the frequency dependence of both the capacitance and conductance in the strong-accumulation condition.…”

mentioning

confidence: 99%

Characterization of near-interface traps at 4H-SiC metal–oxide–semiconductor interfaces using modified distributed circuit model

Zhang

Okamoto

Hatakeyama

et al. 2017

Appl. Phys. Express

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We characterized the near-interface traps (NITs) in SiO2/4H-SiC structures according to the distributed circuit model, which was originally proposed for Al2O3/InGaAs interface structures. We assumed that the NITs had an exponentially decaying distribution from the SiO2/4H-SiC interface into the oxide, rather than the uniform trap distribution of the conventional model. Using this model with the exponential NIT distribution as a basis, we successfully explained the frequency-dependent characteristics of both the capacitance and conductance in the strong-accumulation condition with reasonable physical parameters. We also observed that nitridation annealing over a long period of time significantly reduced the NIT density distribution.

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“…Such a relatively long interval is not recommended in terms of precise evaluation of the instability of V th [36]. Due to the long interval, the amount of charges with a fast detrapping time constant cannot be evaluated by our measurement procedure [35]. In other words, obtained results in this study show the effect of charges with a slow time constant on the radiation response of MOSFETs.…”

Section: Discussionmentioning

confidence: 98%

“…Nevertheless, remarkable increase of σ p J p was not observed and the annealing effect was not extracted from the fitting results. These suggest that most of the hole traps are located close to the SiC/SiO 2 interface [35]. Due to the suppression of movement of holes toward the interface by negatively large E ox , a portion of holes generated by irradiation could be trapped.…”

Section: Discussionmentioning

confidence: 99%

Radiation Response of Negative Gate Biased SiC MOSFETs

et al. 2019

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Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are expected as power electronic devices for high radiative conditions, including nuclear plants and space. Radiation response of commercial-grade prototype SiC MOSFETs with applying the gate bias is of interest, in terms of installation of the device in robots or sensors working under such radioactive circumstances. Due to gamma-rays irradiation, the threshold voltages (Vth) of samples with un- and negative-biased up to −4.5 V slightly shift toward the negative voltage side. In contrast, the positive bias of 2.25 V shifts Vth more negatively. Positive charge densities trapped in the gate oxide of un- and positive-biased samples increased with increasing dose. However, no significant increase was observed for negative-biased samples of −2.25 and −4.5 V. We calculated characteristic parameters for the accumulation of holes in the gate oxide, σpJp which is defined as the product of current density due to holes generated by irradiation and capture cross section for a hole in a trap, and it is lower for these negative biased samples compared with the unbiased case. Application of appropriate negative gate biases to SiC MOSFETs during irradiation suppresses accumulation of positive charges in the gate oxide and negative shift of Vth, due to irradiation.

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Threshold-voltage instability in 4H-SiC MOSFETs with nitrided gate oxide revealed by non-relaxation method

Cited by 28 publications

References 27 publications

Defect engineering in SiC technology for high-voltage power devices

Defect engineering in SiC technology for high-voltage power devices

Characterization of near-interface traps at 4H-SiC metal–oxide–semiconductor interfaces using modified distributed circuit model

Radiation Response of Negative Gate Biased SiC MOSFETs

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