We demonstrated a fast-capacitance-voltage (CV) method for the evaluation of the number and location of holes trapped in a 4H-SiC MOS device under negative gate bias stress. The number of trapped holes was carefully estimated by suppressing recombination and detrapping during stress relaxation. It was found that a large number of holes trapped in a short stress time were reduced by nitridation, and that the hole trapping in a longstress-time region was accelerated by increases in temperature and electric field for a stress. From the results, we determined the respective model for hole trapping and detrapping.

We investigated methods of measuring the threshold voltage (V th ) shift of 4H-silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) under positive DC, negative DC, and AC gate bias stresses. A fast measurement method for V th shift under both positive and negative DC stresses revealed the existence of an extremely large V th shift in the short-stress-time region. We then examined the effect of fast V th shifts on drain current (I d ) changes within a pulse under AC operation. The fast V th shifts were suppressed by nitridation. However, the I d change within one pulse occurred even in commercially available SiC MOSFETs. The correlation between I d changes within one pulse and V th shifts measured by a conventional method is weak. Thus, a fast and in situ measurement method is indispensable for the accurate evaluation of I d changes under AC operation.