Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

Abstract

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Analysis of Dislocation Structures in 4H‐SiC by Synchrotron X‐Ray Topography

“…In other words, a rough unevenness occurred on the epitaxy film surface. In fabrication of MOS structure, it is known that latent scratches cause dielectric breakdown due to the roughness of the step-bunching, which leads to a low yield [11]. We investigated the cause of latent scratches based on Berg-Barrett X-ray topography [5].…”

“…Due to modification of the wafer off-angles and the epitaxy film growth technology in recent years, however, such dislocation pits are no longer a significant factor of the MOS structure dielectric breakdown, though they are still observed. Today, step-bunching on the epitaxy film surface and different uneven structures on the epitaxy film surface are the main causes of the MOS structure dielectric breakdowns [11,38]. Additionally, it is reported that the TDDB characteristic of the MOS capacitor is improved when the epitaxy film surface is smoothened by CMP and then thermally oxidized [42].…”

Characterization of comet-shaped defects on C-face 4H-SiC epitaxial wafers by electron microscopy

“…However, several types of defects still remain in 4H-SiC epitaxial films on 41 off-axis Si-face wafers, such as 3C-particles and triangular defects, which have a negative impact on the electrical properties of the device [1,2]. Not only these such defects, but also various surface defects, which consist of step-bunchings on the Si-face, are recently reported to have a serious and negative impact on the dielectric breakdown of metal oxide semiconductors (MOS) [3][4][5].…”

The Origin and Formation Mechanism of an Inclined Line‐like Defect in 4H‐SiC Epilayers

“…Recent studies have shown that there is a clear correlation between surface morphological defects and the failure rate of 4H-SiC Schottky barrier diodes (SBDs) and metalÀoxideÀsemiconductor field-effect transistors (MOSFETs). [24,25] As the negative effect comes from geometrical considerations of the morphological defects, [26] that is, electric field crowding, most of the surface morphological defects would probably have a similar effect on SBDs and MOSFETs. It is therefore important to understand how and why morphological defects form during the growth and postgrowth processing of 4 H-SiC epitaxial layers.…”