The design of a high-speed IC random number source macro-cell, suitable to be integrated in a Smart Card microcontroller, is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise source has been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillator feedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. A numerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transition probability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital 0:18"m n-well CMOS process which features a 10Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. The macro-cell area, excluding pads, is 0:0016mm 2 (184"m  86"m) and a 2:3mW power consumption has been measured.

This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.

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A new current mode building block named voltage and current gain second generation current conveyor (VCG-CCII) is introduced. The voltage and current buffers of the standard CCII are replaced by voltage and current amplifiers with tunable gains so to obtain an extremely flexible and versatile building block. The VCG-CCII can be used in place of the standard CCII in impedance conversion applications so to utilize only one active component. A circuit implementation in a standard 0.35 lm CMOS process is presented and used to multiply, as an example, a 10 pF capacitor by a factor tunable from 1 up to about 3100, achieving a capacitance multiplication for more than 6 decades frequency range (from 0.15 to 865 KHz for the highest multiplication factor).

Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic processors. In this paper, a countermeasure against DPA is presented and evaluated on a case study simulation. It can be implemented, using a standard digital technology, by applying a straightforward transformation to the original design, without an actual redesign. A methodology to perform a DPA in simulation is presented which can be exploited to test the resistance of a cryptographic processor during its design flow. By using the above methodology, the proposed countermeasure shows a 30dB attenuation of the signals exploited by the DPA.

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SUMMARYThe body-driven variant of the gain-boosting technique is here exploited to design a CMOS transconductance amplifier with minimum supply below 1 V. When compared with the conventional gain-boosting technique, the proposed body-driven approach reduces the minimum supply requirement by two thresholds in a rail-to-rail amplifier exploiting two complementary input stage topologies. Simulations using a 130-nm process show that a 0.9-V power supply is adequate for a single-stage rail-to-rail amplifier providing a 56-dB gain, which is 18 dB higher than that achieved by the same architecture but using the traditional cascoding approach. The main drawbacks are that the solution requires a twin-tub process and an additional bias section.