A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors

Bucci, Marco; Guglielmo, M.; Luzzi, R.; Trifiletti, Alessandro

doi:10.1007/978-3-540-30205-6_50

Cited by 39 publications

(29 citation statements)

References 9 publications

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“…The flow supports partitioning of a design between CMOS and protected logic, and includes a sound metric to measure resistance against side-channel attacks. Figure 1 depicts the design flow, which is an extension of prior simulationbased methodologies to evaluate resistance to power analysis attacks [6,22]. The key idea is to use commodity from EDA tools and to leverage on transistor level simulation to provide a high degree of accuracy.…”

Section: The Proposed Hybrid Design Flowmentioning

confidence: 99%

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Regazzoni

Cevrero

Standaert

et al. 2009

Lecture Notes in Computer Science

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Abstract. Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.

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Section: The Proposed Hybrid Design Flowmentioning

confidence: 99%

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

Regazzoni

Cevrero

Standaert

et al. 2009

Lecture Notes in Computer Science

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“…In this project we describe a new flexible integrated simulation-based environment that allows validating a digital circuit when the device is attacked by means of this attack. With respect to the one proposed in [2], and with respect to all the custom-solutions implemented for a specific design, our solution allows to set most of the parameters and features (e.g., power consumption models, observation mechanisms, and statistical analysis) in such a way that different forms of DPA can be experimented. Then it generates the scripts required to perform the transistor level simulation of the circuit for a user defined vector set.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Validation Environment for Differential Power Analysis

Natale

Flottes

Rouzeyre

2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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“…This measure can be implemented solely by careful modification of the cryptographic software, but delivers at best a moderate increase in security. A similar countermeasure was proposed in [3] for hardware implementations.…”

Section: Option 2: Random Prechargingmentioning

confidence: 99%

Power Analysis Resistant AES Implementation with Instruction Set Extensions

Tillich

Großschädl

Cryptographic Hardware and Embedded Systems - CHES 2007

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Abstract. In recent years, different instruction set extensions for cryptography have been proposed for integration into general-purpose RISC processors. Both public-key and secret-key algorithms can profit tremendously from a small set of custom instructions specifically designed to accelerate performance-critical code sections. While the impact of instruction set extensions on performance and silicon area has been widely investigated in the recent past, the resulting security aspects (i.e. resistivity to side-channel attacks) of this particular design approach remain an open research topic. In this paper we discuss and analyze different techniques for increasing the side-channel resistance of AES software implementations using instruction set extensions. Furthermore, we propose a combination of hardware and software-related countermeasures and investigate the resulting effects on performance, cost, and security. Our experimental results show that a moderate degree of protection can be achieved with a simple software countermeasure. Hardware countermeasures, such as the implementation of security-critical functional units using a DPA-resistant logic style, lead to much higher resistance against side-channel attacks at the cost of a moderate increase in silicon area and power consumption.

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A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors

Cited by 39 publications

References 9 publications

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

An Integrated Validation Environment for Differential Power Analysis

Power Analysis Resistant AES Implementation with Instruction Set Extensions

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