Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic processors. In this paper, a countermeasure against DPA is presented and evaluated on a case study simulation. It can be implemented, using a standard digital technology, by applying a straightforward transformation to the original design, without an actual redesign. A methodology to perform a DPA in simulation is presented which can be exploited to test the resistance of a cryptographic processor during its design flow. By using the above methodology, the proposed countermeasure shows a 30dB attenuation of the signals exploited by the DPA.

Differential power analysis is widely recognized as an extremely powerful and low-cost technique to extract secret information from cryptographic devices. As a consequence, DPA-countermeasures have been proposed in the technical literature ranging over every abstraction level in an embedded system, from software to transistor-level techniques. In this paper, a novel gate-level countermeasure is proposed which, exploiting the insertion of random delays in the datapath of a cryptographic processor, allows to randomize not just the instantaneous current consumption profile but also the total charge quantity transferred from the power supply during a clock cycle.