Three-Phase Dual-Rail Pre-charge Logic

Abstract

This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

“…In contrast, the TDPL NAND/AND logic [8] in Fig. 3(a) was implemented using universal dual-rail pull-down network tree.…”

“…In responding to the SCA attacks, several works on the cell level have been reported by the sense amplifier based logic (SABL) [7], three-phase dual-rail pre-charged logic (TDPL) [8]. Among those implemented logic styles in the cell library, majority of them applied conventional CMOS logic operation that causes the high spike current occurrence and huge energy consuming.…”

Divided Backend Duplication Methodology for Balanced Dual Rail Routing

“…It is also possible to use a Domino-style inverter (similar to the one presented in [13]) instead of an XOR gate. As in the case of the XOR, prch is used to precharge the domino-inverter.…”

“…To address the routing problem, to date the following proposals have been put forward: DWDDL [3], FatWire [1], Backend Duplication [2], Three Phase Dual Rail [13], Path Switching [9], Double WDDL [14] and an iterative correction flow [15]. Of these, three proposals [1,2,3] impose some constraints on backend implementation flows.…”

“…Of these, three proposals [1,2,3] impose some constraints on backend implementation flows. Three Phase Dual Rail [13] tries to avoid the routing problem by introducing a third phase, which is an additional overhead. Path Switching [9] offers an improvement to dual rail circuits and only protects registers and buses with high capacitance.…”