This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.
This paper investigates the design of a data flip-flop compatible with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption, an additional discharge phase is performed after pre-charge and evaluation. In this work, the TDPL basic gates operation is shortly summarized and the TDPL flip-flop implementation is reported. A part of an encryption algorithm is used as case a study to prove the effectiveness of the proposed circuit. Simulation results in a 65 nm CMOS process show an improvement in the energy consumption balancing in excess of 10 times with respect to the state of the art.Index Terms-Differential power analysis (DPA), dual-rail logic, security, sense amplifier-based logic (SABL), three-phase dual-rail pre-charge logic (TDPL).
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