Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits

Alioto, Massimo; Giancane, L.; Scotti, Giuseppe; Trifiletti, Alessandro

doi:10.1109/tcsi.2009.2019411

Cited by 97 publications

(48 citation statements)

References 13 publications

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“…This illustrates the dep current on input patterns. The same observed in PMOS transisto exploited to wage leakage-bas cryptographic systems [3,4,19]. T of LPA will be explained in the nex …”

Section: ) Leakage Power Dependency On Input Pmentioning

confidence: 63%

“…This trend has led to the creation of a novel class of side channels attacks (SCA) on cryptographic circuits, which exploits the dependency of the leakage current of CMOS integrated circuits on their input patterns to deduce the secret key [2], they are called leakage power attacks (LPA). Several types of LPA's have recently been reported to be successful [3,4]. The first is called leakage differential power analysis (LDPA); it is based on the correlation between a set of leakage power measurements and a selection function related to the key.…”

Section: Introductionmentioning

confidence: 99%

“…The first is called leakage differential power analysis (LDPA); it is based on the correlation between a set of leakage power measurements and a selection function related to the key. A second form of LPA is based on the correlation between the Hamming weight of the inputs of crypto cores and their corresponding set of static power measurements [3]. The latter is going to be referred to in this paper as leakage-based Hamming weight power analysis (LHPA).…”

Section: Introductionmentioning

confidence: 99%

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Power balanced circuits for leakage-power-attacks resilient design

Halak

Murphy

Yakovlev

2015

2015 Science and Information Conference (SAI)

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The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. The latter exploits the correlation between leakage current and the input patterns to infer the secret key; it is called leakage power analysis (LPA). The use power-balanced (m-of-n) logic is a promising solution that provides an answer to this problem, such circuits are designed to consume constant amount of power regardless of data being processed. This work evaluates the security of cryptographic circuits designed with this technology against the newly developed LPA. Two forms of LPA are investigated, one is based on differential power analysis (LDPA) and the other based on Hamming weight analysis (LHPA). Simulations performed at 90nm CMOS technology reveal that (m-of-n) circuits are totally resilient to LHPA and have a higher security level against LDPA than standard logic circuits.

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Section: ) Leakage Power Dependency On Input Pmentioning

confidence: 63%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Power balanced circuits for leakage-power-attacks resilient design

Halak

Murphy

Yakovlev

2015

2015 Science and Information Conference (SAI)

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“…However, when using smaller feature length CMOS technology such as 65 nm technology, leakage power accounts for at least 20% to 30% of the total power consumption [2], [24]- [27]. Therefore, an estimation of the scaled power consumption at 65 nm technology could be expressed by (26) assuming that the leakage power is 20% of the dynamic power. (26) The authors in [18] and [21] proposed 64-QAM MIMO detector design based on the K-Best approach.…”

Section: E Comparison With Previous Workmentioning

confidence: 99%

“…Therefore, an estimation of the scaled power consumption at 65 nm technology could be expressed by (26) assuming that the leakage power is 20% of the dynamic power. (26) The authors in [18] and [21] proposed 64-QAM MIMO detector design based on the K-Best approach. The work in [18] achieves comparable processing throughput with the proposed architecture with less area and power consumption since the proposed scheme contains the additional feature of achieving error-resilience.…”

Section: E Comparison With Previous Workmentioning

confidence: 99%

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems

Khairy

Shen

Eltawil

et al. 2014

IEEE Trans. Circuits Syst. I

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Abstract-In a broadband MIMO-OFDM wireless communication system, embedded buffering memories occupy a large portion of the chip area and a significant amount of power consumption. Due to process variations of advanced CMOS technologies, it becomes both challenging and costly to maintain perfectly functioning memories under all anticipated operating conditions. Thus, Voltage over Scaling (VoS) has emerged as a means to achieve energy efficient systems resulting in a tradeoff between energy efficiency and reliability. In this paper we present the algorithm and VLSI architecture of a novel error-resilient K-Best MIMO detector based on the combined distribution of channel noise and induced errors due to VoS. The simulation results show that, compared with a conventional MIMO detector design, the proposed algorithm provides up-to 4.5 dB gain to achieve the near-optimal Packet Error Rate (PER) performance in the 4 4 64-QAM system. Furthermore, based on experimental results, when jointly considering the detector and memory power consumption, the proposed resilient scheme with VoS memory can achieve up to 32.64% savings compared to the conventional K-Best detector with perfect memory.Index Terms-MIMO detector, MIMO OFDM, SRAM, VLSI, voltage over scaling, wireless communication.

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Template attacks exploiting static power and application to CMOS lightweight crypto‐hardware

Bellizia

Djukanović

Scotti

et al. 2016

Circuit Theory & Apps

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A new class of template attacks aiming at recovering the secret key of a cryptographic core from measurements of its static power consumption is presented in this paper. These attacks exploit the dependence of the static current of Complementary metal–oxide–semiconductor Integrated Circuits on the input vector and the maximum likelihood decision rule as a statistical distinguisher. In the proposed Template Attacks Exploiting Static Power (TAESP), we take advantage of the temperature dependence of static currents in order to build a new multivariate approach able to extract relevant information from cryptographic devices. As a validation case study, we consider the PRESENT-80 block cypher algorithm and its implementation on a 40 nm Complementary metal–oxide–semiconductor process. Monte Carlo and corner simulations at transistor level are used to show the effectiveness of the TAESP in the presence of die-to-die and intra-die process variations. A real attack scenario is then built by adding Gaussian noise to current samples extracted from transistor-level simulations. The univariate TAESP in which just one temperature is considered to build the templates is compared against the multivariate TAESP in which measurements at different controlled temperatures are exploited. This comparison shows that using just a few different temperatures to build multivariate templates allows to strongly increase the effectiveness of the attack. Copyright © 2016 John Wiley & Sons, Ltd

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Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits

Cited by 97 publications

References 13 publications

Power balanced circuits for leakage-power-attacks resilient design

Power balanced circuits for leakage-power-attacks resilient design

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems

Template attacks exploiting static power and application to CMOS lightweight crypto‐hardware

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