As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.
Abstract-Graphic Processing Units (GPUs) have evolved to provide a massive computational power. In contrast to Central Processing Units, GPUs are so-called many-core processors with hundreds of cores capable of running thousands of threads in parallel. This parallel processing power can accelerate the simulation of communication systems. In this work, we utilize NVIDIA's Compute Unified Device Architecture (CUDA) to execute two different sphere decoders on a graphic card. Both flat fading and frequency selective channels are considered. We find that the execution of the soft-sphere decoder can be accelerated by factors of 6-8, and the fixed-complexity sphere decoder even by a factor of 50.
Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders.
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