0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair

Grasso, Alfio Dario; Pennisi, S.; Scotti, Giuseppe; Trifiletti, Alessandro

doi:10.1109/tcsi.2017.2681964

Cited by 53 publications

(34 citation statements)

References 27 publications

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“…less than two threshold voltages. A threshold lowering technique [7] has been exploited for the transistors operating in the subthreshold region, to optimise the bias point and reduce the transistor size (and hence input capacitance) for a given bias current. Due to the low supply voltage, less than the turn‐on voltage of pn junctions, the body terminal of NMOS devices ( M 1 , M 2 , M 2 A , M 13 ) is connected to the positive supply rail and that of PMOS devices ( M 4 , M 5 , M 5 A , M 9 ) to the negative supply rail, and this allows reducing the threshold voltage of about 85 mV (i.e.…”

Section: Simulation Resultsmentioning

confidence: 99%

A 0.6 V class‐AB rail‐to‐rail CMOS OTA exploiting threshold lowering

et al. 2018

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A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration.

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Section: Simulation Resultsmentioning

confidence: 99%

A 0.6 V class‐AB rail‐to‐rail CMOS OTA exploiting threshold lowering

et al. 2018

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“…This result can be achieved by exploiting transistors with different threshold voltages (which are now available in all advanced CMOS processes) or using a suitable body bias to lower the value of the threshold voltage of M2, as shown in Figure 2, through bias voltage VB. 10,11 The maximum voltage that can be applied to the body of M2 is limited by the body-source junction that has to remain reverse biased. This is however not a concern for very low-voltage applications.…”

Section: Proposed Gain Boosting Approachmentioning

confidence: 99%

0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias

Cellucci

Centurelli

Stefano

et al. 2019

Circuit Theory & Apps

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An innovative low-voltage low-power complementary metal-oxidesemiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate-driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch. The solution is also exploited in a rail-to-rail high-performance single-stage cascode operational transconductance amplifier (OTA). Simulations using a 40-nm process with thresholds around 0.45 V show that 0.6 V and 50 μA are adequate to supply the designed OTA, which exhibits a 60-dB direct current (DC) gain, a 45-MHz unity-gain frequency, and an 18-V/μs slew rate, under a 1-pF load.

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“…Although bulk-driven circuits offer extended input voltage range in low-voltage design, they still have many problems like high input noise, increased area, high offset voltage, increased mismatches, and low gain-bandwidth [11][12][13][14][15][16][17][18][19][20][21][22]. These problems become prominent due to increased input capacitance and low transconductance.…”

Section: Introductionmentioning

confidence: 99%

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

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An efficient architecture of a high-performance ultra-low-voltage gate-driven two-stage pseudo-fully differential operational transconductance amplifier (OTA) is presented. The proposed subthreshold-region operated OTA utilizes two identical conventional current-mirror-based source coupled pseudo-differential amplifiers with their cross-connected gate as core amplifier blocks. The input core differential pair exploiting forward body terminal biasing scheme at output load employed in cascaded stages essentially improves the overall transconductance more than twice compared to the conventional pseudo-differential pair based OTA and achieves near rail-to-rail output voltage swing (90.2% of supply voltage) for near rail-to-rail input common-mode voltage (94.92% of supply voltage). The circuit is designed and optimized using g m /I D technique associated with the Particle Swarm Optimization (PSO) algorithm with a single supply of 0.35 V for a capacitive load of 10 pF and simulated in Cadence Virtuoso analog environment using UMC 180-nm CMOS technology. Post-layout simulations have been accomplished to justify the performance of the proposed OTA. It achieves an open-loop gain of 83.00 dB, phase margin of 61.48°, and power dissipation of 35.04 nW at a unity gain frequency of 24.78 kHz. A low-frequency continuous second-order G m -C filter is also implemented to validate its workability. Simulation results of this work are compared to the state-of-the-art architecture available, and enhanced performance is validated. Keywords Operational transconductance amplifier (OTA) Á Unity gain frequency (UGF) Á Subthreshold region Á Input common-mode range (ICMR) Á Biquad G m -C filter & Sougata Ghosh

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0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair

Cited by 53 publications

References 27 publications

A 0.6 V class‐AB rail‐to‐rail CMOS OTA exploiting threshold lowering

A 0.6 V class‐AB rail‐to‐rail CMOS OTA exploiting threshold lowering

0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

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